UPD16780 データシートの表示（PDF） - NEC => Renesas Technology
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UPD16780 Datasheet PDF : 16 Pages
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µ PD16780
4. PIN FUNCTIONS
Pin Symbol
Pin Name
Description
C1,C2,C3
Video signal input
These pins are input video signals R,G, and B.
S1-S300
Video signal input
STHR,
STHL
Cascade I/O
These pins are output video signals, which have been sampled and hold.
C1: S3n-2 (n = 1, 2, ··········96/100)
C2: S3n-1
C3: S3n
These pins are inputs/outputs for the start pulse for sample and hold timing.
High level of STHR/STHL is read at rising edge of CLK and start sampling video signal.
STHR serves as the input pin and STHL serves as output pin for the right shift. For left
• R,/L
Shift direction switching
input
shift, STHL serves as the input pins and STHR serves as the output pin.
The shift directions of the shift registers are as follows.
R,/L = H: STHR input, S1 → S300, STHL output.
R,/L = L: STHL input, S300 → S1, STHR output.
Osel
Selection of Number of Selects number of outputs.
outputs switching input Osel = L: 288 output mode
Osel = H: 300 output mode
Output pins S145 through S156 are invalid in 288 output mode.
The signal which is with S157 to S168 (R,/L = H) or S133 to S144 (R,/L = L) is output
CLK
Shift clock input
identically.
The start pulse is read at rising edge of CLK. The sampling pulse SHPn is generated
at rising edge of CLK.
µ PD16780 corresponds only to LCD of Stripe array color filter and only simultaneous
sampling. For details, refer to 6. TIMING CHART.
CX
Hold capacitance control Two Sample & hold circuits are switched.
input
CX = H S&H1: Sampling, S&H2: Output
TEST
VDD1
VDD2
VSS1
VSS2
VSS3
Test pin
Logic power supply
Driver power supply
Logic ground
Driver ground
Sample & hold ground
CX = L S&H1: Output, S&H2: Sampling
Fix this pin to the L level.
3.3 V ± 0.3 V, or 5.0 V ± 0.5 V
5.0 V ± 0.5 V
Grounding
Grounding
It is ground of Sample & hold capacitance. Supply this terminal with the stable GND.
4
Data Sheet S12608EJ1V0DS00
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