UPD16781 データシートの表示（PDF） - NEC => Renesas Technology

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UPD16781

480 OUTPUT TFT-LCD SOURCE DRIVER

NEC => Renesas Technology 

µ PD16781

4. PIN FUNCTIONS

Pin Symbol

C1 to C3

S1 to S480

Pin Name

Video signal input

Video signal output

STHR,

STHL

Cascade I/O

R,/L

Shift direction control

CLK1 to CLK3 Shift clock input

I/O

Description

I

These pins are input video signals R, G, and B.

O These pins are output video signals, which have been sampled and hold.

The relationship between the video signal input (C1 to C3) and video signal output is

shown below.

C1: S3n−2 (n = 1, 2, ··········160)

C2: S3n−1

C3: S3n

I/O These pins are inputs/outputs for the start pulse for sample and hold timing.

High level of STHR/STHL is read at rising edge of CLK and start sampling video

signal. STHR serves as the input pin and STHL serves as output pin for the right

shift. For left shift, STHL serves as the input pins and STHR serves as the output

pin.

I

The shift direction control pin of shift register. The shift directions of the shift

registers are as follows.

R,/L = H (right shift): STHR input, S1 → S480, STHL output.

R,/L = L (left shift): STHL input, S480 → S1, STHR output.

I

The start pulse is read at rising edge of CLK. The sampling pulse SHPn is

generated at rising edge of CLK. For details, refer to 6. TIMING CHART.

The relationship between the clocks and the output pins is shown below.

(1) When MODE = L or open (sequential sampling)

CLK1 R,/L = H: S3n−2

R,/L = L: S3n

CLK2: S3n−1

CLK3 R,/L = H: S3n

R,/L = L: S3n−2

(1) When MODE = H (simultaneous sampling)

CLK1: S3n−2, S3n−1, S3n (n = 1, 2,·····160)

CLK2: Connect VDD1 or VSS1

CLK3: Connect VDD1 or VSS1

MODE

CX

TEST

VDD1

VDD2

VSS1

VSS2

VSS3

Mode select signal input

I

This pin is used to select whether the three analog input signals, C1, C2, and C3 are

sampled simultaneously or sequentially (This pin is pulled down in the IC).

MODE = H: Simultaneous sampling

MODE = L or open: Sequential sampling

Hold capacitance control

I

Two Sample & hold circuits are switched.

input

CX = H S&H1: Sampling, S&H2: Output

CX = L S&H1: Output, S&H2: Sampling

Test

I

Fix this pin to the L level.

Logic power supply

− 3.0 to 5.5 V

Driver power supply

− 5.0 ± 0.5 V

Logic ground

− Grounding

Driver ground

− Grounding

Sample & hold ground

− It is ground of Sample & hold capacitance. Supply this terminal with the stable

GND.

4

DataSheet S14634EJ1V0DS

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