UPD161641N データシートの表示（PDF） - NEC => Renesas Technology
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UPD161641N Datasheet PDF : 15 Pages
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µPD161641
3. PIN FUNCTIONS
Symbol
O1 to O240
Pin Name
Driver output
Pad No.
132 to 251,
258 to 377
STVR,
STVL
Start pulse input/output 85 to 89,
91 to 95
STVSEL
Start pulse input
33 to 37
effective level selection
CLK
Shift clock input
97 to 101
R,/L
OE1
Shift direction
switching input
Enable input
39 to 43
103 to 107
OE1SEL
OE1 effective level
selection
OE2
Enable input
20 to 24
109 to 113
OE2SEL
OE2 effective level
selection
26 to 30
I/O
Output
I/O
Input
Input
Input
Input
Input
Input
Input
(1/2)
Function
Scan signal output pins that drive the gate electrode of a TFT-
LCD. The status of each output pin changes in synchronization
with the rising edge of shift clock. The output voltage of the driver
is VT-VB.
Input/output pin of the internal shift register.
Read of start pulse signal is set at rising edge of shift clock, and
outputs a scanning signal from a driver output pin. In addition,
the effective level of a STVR/STVL pin is determined by setup
of STVSEL pin. Moreover, an input/output level is VCC1-VSS
(logic level).
STVSEL = L: Start pulse is set to low level by the 240th falling
edge of shift clock, and is set to a high level by the 241st falling
edge.
The effective level of the start pulse signal inputted into
STVR/STVL is selected.
STVSEL = L: Low level
STVSEL = H: High level
Shift clock input for the internal shift register. The contents of
internal shift register is shifted at the rising edge of CLK.
Connect to GCLK pin of source driver.
Shift direction switching input pin of the internal shift register.
R,/L = H (right shift): STVR → O1 → O2 ··· O239 → O240 → STVL
R,/L = L (left shift): STVL → O240 → O239 ··· O2 → O1 → STVR
Input of the level selected by OE1SEL fixes a driver output to a
low level (input of a low level fixes driver output to low level at
the time of OE1SEL = L). However, shift register is not cleared.
Moreover, output enable operation is asynchronous on a clock.
Connect with GOE1 pin of sauce driver.
This pin selects effective level of OE1 pin.
OE1SEL = L: Low level
OE1SEL = H: High level
Input of the level selected by OE2SEL fixes a driver output to a
high level (input of a low level fixes driver output to high level at
the time of OE2SEL = L). However, shift register is not cleared.
Moreover, output enable operation is asynchronous on a clock.
Connect with GOE2 pin of sauce driver.
This pin selects effective level of OE2 pin.
OE2SEL = L: Low level
OE2SEL = H: High level
8
Data Sheet S15678EJ1V0DS
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