UPD161660 データシートの表示（PDF） - NEC => Renesas Technology

部品番号

コンポーネント説明

メーカー

UPD161660

POWER SUPPLY FOR TFT-LCD DRIVER

NEC => Renesas Technology 

µPD161660

that the gate output may be undefined and the DC/DC converter and the regulators may be on. If the B period is

sufficiently short however, it is unlikely that the display will be affected. Note that the gate output MAX value in the

B period must be determined separately as a specification of the LCD module.

 The pins are re-fixed to the following levels by the source driver when the RESET command is input.

Note that the gate output is fixed to the VB level, and the DC/DC converter and the regulators are off.

DCON, RGONG, RGONP, OE1: L (low level)

OE2: H (high level)

~ Set a timing that ensures the DCON, RGONP, and RGONG pins are shifted to high level in that order after the

RESET command is input. At this time, the DC/DC converter and the regulators are on. Before that, the booster

level must have been set up (by BGRS, VCE, VCD2, PVCOM of R32 register and R34 register of the µPD161620) .

Note that the target timing of tDDRP and tRPRG (while the DC/DC converter output and regulator output is stable) is

tDDRP = approx. 50 ms and tRPRG = approx. 20 ms, but users are requested to set the final timing after sufficiently

evaluating the µPD161660 in the LCD module.

 Input the DISPON command (↑part) after ensuring that all the power supplies are high level.

The source driver will start display with OE1 = H.

The target is tRGOE1 = approx. 1 ms, but users are requested to set the final timing after sufficiently evaluating the

µPD161660 in the LCD module.

Data Sheet S14799E1V0DS

11

Share Link: