D43257B データシートの表示（PDF） - NEC => Renesas Technology

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D43257B

256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT

NEC => Renesas Technology 

µPD43257B

Write Cycle Timing Chart 1 (/WE Controlled)

Address (Input)

/CE1 (Input)

CE2 (Input)

/WE (Input)

I/O (Input / Output)

tWC

tCW1

tCW2

tAW

tAS

tWP

tWR

tWHZ

Indefinite data out

High

impe-

dance

tOW

tDW

tDH

Data in

High

impe-

dance

Indefinite data out

Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.

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2. When I/O pins are in the output state, therefore the input signals must not be applied to

the output.

Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2.

2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2

changes to high level at the same time or after the change of /WE to low level, the I/O pins will

remain high impedance state.

3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,

read operation is executed. Therefore /OE should be at high level to make the I/O pins high

impedance.

Data Sheet M10693EJ7V0DS00

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