UPD750006CUA データシートの表示（PDF） - NEC => Renesas Technology
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UPD750006CUA Datasheet PDF : 84 Pages
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µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)
3.2 NON-PORT PINS
Pin name
TI0
PTO0
PTO1
PCL
BUZ
SCK
SO/SB0
SI/SB1
INT4
INT0
INT1
INT2
KR0 - KR3
KR4 - KR7
X1
X2
XT1
XT2
RESET
IC
VDD
VSS
Input/
output
Input
Output
I/O
Input
Input
Input
I/O
I/O
Input
-
Input
-
Input
-
-
-
Shared
pin
Function
P13
Inputs external event pulse to the timer/event
counter
P20
Timer/event counter output
P21
Timer counter output
P22
Clock output
P23
Arbitrary frequency output (for buzzer output or
system clock trimming)
P01
Serial clock I/O
P02
Serial data output
Serial data bus I/O
P03
Serial data input
Serial data bus I/O
P00
Edge detection vectored interrupt input (both
rising and falling edges are detected)
P10
Edge detection vectored interrupt input
Note 2
(detection edge selectable). A noise eliminator
P11
can be selected when INT0/P10 is used.
Note 3
P12
Rising edge detection testable input
Note 3
P60 - P63 Falling edge detection testable input
P70 - P73 Falling edge detection testable input
-
Crystal/ceramic connection pin for main system
clock generation. When external clock signal is
used, it is applied to X1, and its reverse phase
signal is applied to X2.
-
Crystal connection pin for subsystem clock
generation. When external clock signal is used, it
is applied to XT1, and it reverse phase signal is
applied to XT2.
XT1 can be used as a 1-bit input (test).
-
System reset input (active low)
-
Internally connected. (To be connected directly to
VDD)
-
Positive power supply
-
Ground potential
When reset
Input
Input
Input
Input
Input
Input
-
-
-
-
-
-
I/O circuit
typeNote 1
B -C
E-B
F -A
F -B
M -C
B
B -C
F -A
F -A
-
-
B
-
-
-
Notes 1. The circle ( ) indicates the Schmitt trigger input.
2. With a noise eliminator/asynchronously selectable
3. Asynchronous
10
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