UPD75008 データシートの表示（PDF） - NEC => Renesas Technology

部品番号

コンポーネント説明

メーカー

UPD75008

4-BIT SINGLE-CHIP MICROCOMPUTER

NEC => Renesas Technology 

µPD75004, 75006, 75008

4. MEMORY CONFIGURATION

• Program memory (ROM) ... 4096 × 8 bits (0000H-0FFFH) : µPD75004

... 6016 × 8 bits (0000H-177FH) : µPD75006

... 8064 × 8 bits (0000H-1F7FH) : µPD75008

• 0000H-0001H : Vector table to which address from which program is started is written after reset

• 0002H-000BH: Vector table to which address from which program is started is written after interrupt

• 0020H-007FH : Table area referenced by GETI instruction

• Data memory (RAM)

• Data area .... 512 × 4 bits (000H–1FFH)

• Peripheral hardware area .... 128 × 4 bits (F80H–FFFH)

Address

7654

000H MBE 0 0 0 Internal reset start address (upper 4 bits)

Internal reset start address (lower 8 bits)

002H MBE 0 0 0 INTBT/INT4 start address (upper 4 bits)

INTBT/INT4 start address (lower 8 bits)

004H MBE 0 0 0 INT0 start address (upper 4 bits)

INT0 start address (lower 8 bits)

006H MBE 0 0 0 INT1 start address (upper 4 bits)

INT1 start address (lower 8 bits)

008H MBE 0 0 0 INTCSI start address (upper 4 bits)

INTCSI start address (lower 8 bits)

00AH MBE 0 0 0 INTT0 start address (upper 4 bits)

INTT0 start address (lower 8 bits)

0

CALLF

!faddr

instruction

entry

address

CALL ! addr

instruction

subroutine

entry address

BRCD ! caddr

instruction

branch address

020H

07FH

080H

GETI instruction reference table

BR $addr

instruction

relational

branch address

(–15 to –1,

+2 to +16)

7FFH

800H

Branch destination

address and

subroutine entry

address for

GETI instruction

FFFH

16

Fig. 4-1 Program Memory Map (µPD75004)

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