UPD75008 データシートの表示（PDF） - NEC => Renesas Technology

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UPD75008

4-BIT SINGLE-CHIP MICROCOMPUTER

NEC => Renesas Technology 

µPD75004, 75006, 75008

5.2 CLOCK GENERATOR CIRCUIT

The operation of the clock generator circuit is determined by the processor clock control regiser (PPC) and

system clock control register (SCC).

This circuit can generate two types of clocks: main system clock and subsystem clock.

In addition, it can also change the instruction execution time.

• 0.95 µs, 1.91 µs, 15.3 µs (main system clock: 4.19 MHz)

• 122 µs (subsystem clock: 32.768 kHz)

5

XT1

Subsystem

clock

f XT

XT2 oscillator

X1

Main system f X

clock

X2 oscillator

Watch timer

· Basic interval timer (BT)

· Timer/event counter

· Serial interface

· Watch timer

· INT0 noise rejecter circuit

· Clock output circuit

1/8 to 1/4096

Frequency divider

1/2 1/16

WM.3

SCC

SCC3

SCC0

PCC

PCC0

PCC1

4

PCC2

HALT*

PCC3

STOP*

Oscillator

disable

signal

PCC2, PCC3

clear signal

STOP F/F

QS

R

*: instruction execution.

Frequency

divider

1/4 Φ

· CPU

· INT0 noise

rejecter circuit

· Clock output

circuit

HALT F/F

S

RQ

Wait release

signal from BT

RESET signal

Standby release

signal from interrupt

control circuit

Remarks 1: fX = Main system clock frequency

2: fXT = Subsystem clock frequency

3: Φ = CPU clock

4: PCC: Processor clock control register

5: SCC: System clock control register

6: One clock cysle (tCY) of Φ is one machine cycle of an instruction. For tCY, refer to AC

characteristics in 10. ELECTRICAL SPECIFICATIONS.

Fig. 5-1 Clock Generator Block Diagram

21

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