UPD75008 データシートの表示（PDF） - NEC => Renesas Technology

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UPD75008

4-BIT SINGLE-CHIP MICROCOMPUTER

NEC => Renesas Technology 

µPD75004, 75006, 75008

5.8 BIT SEQUENTIAL BUFFER .... 16 BITS

The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer,

addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this

buffer is very useful for processing long data in bit units.

Address bit

FC3H

FC2H

FC1H

FC0H

32

1

0

3

2

10

3

2

1

0

3

2

10

Symbol

BSB3

BSB2

BSB1

BSB0

L register L = F

L=C L=B

INCS L

L=8 L=7

L=4 L=3

DECS L

L=0

Remarks: For the pmem.@L addressing, the specification bit is shifted according to the L register.

Fig. 5-7 Bit Sequential Buffer Format

6. INTERRUPT FUNCTIONS

The µPD75008 has 8 different interrupt sources and multiplexed interrupt through the software control.

In addition to that, the µPD75008 is also provided with two types of edge detection testable inputs.

The interrupt control circuit of the µPD75008 has these functions:

• Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by

using the interrupt flag (IExxx) and interrupt master enable flag (IME).

• The interrupt start address can be arbitrarily set.

• Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of

software).

• Standby mode release (Interrupts to be released can be selected by the interrupt enable flag).

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