UPD750068(A) データシートの表示（PDF） - NEC => Renesas Technology
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UPD750068(A) Datasheet PDF : 82 Pages
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µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
1. PIN CONFIGURATION (Top View)
• 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
µPD750064CU-×××, µPD750064CU(A)-×××
µPD750066CU-×××, µPD750066CU(A)-×××
µPD750068CU-×××, µPD750068CU(A)-×××
• 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
µPD750064GT-×××, µPD750064GT(A)-×××
µPD750066GT-×××, µPD750066GT(A)-×××
µPD750068GT-×××, µPD750068GT(A)-×××
XT1
1
XT2
2
RESET
3
X1
4
X2
5
P33
6
P32
7
P31
8
P30
9
AVSS
10
P63/KR3/AN7
11
P62/KR2/AN6
12
P61/KR1/AN5
13
P60/KR0/AN4
14
P113/AN3
15
P112/AN2
16
P111/AN1
17
P110/AN0
18
AVREF
19
IC
20
VDD
21
42
VSS
41
P40
40
P41
39
P42
38
P43
37
P50
36
P51
35
P52
34
P53
33
P00/INT4
32
P01/SCK
31
P02/SO/SB0
30
P03/SI/SB1
29
P10/INT0
28
P11/INT1
27
P12/TI1/INT2
26
P13/TI0
25
P20/PTO0
24
P21/PTO1
23
P22/PCL
22
P23/BUZ
IC: Internally Connected (Connect pin directly to VDD).
Pin Identification
AN0 to AN7
: Analog Input 0 to 7
AVREF
: Analog Reference
AVSS
: Analog Ground
BUZ
: Buzzer Clock
IC
: Internally Connected
INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4
INT2
: External Test Input 2
KR0 to KR3
: Key Return 0 to 3
P00 to P03
: Port 0
P10 to P13
: Port 1
P20 to P23
: Port 2
P30 to P33
: Port 3
P40 to P43
: Port 4
P50 to P53
: Port 5
P60 to P63
P110 to P113
PCL
PTO0, PTO1
RESET
SB0, SB1
SCK
SI
SO
TI0, TI1
VDD
VSS
X1, X2
XT1, XT2
: Port 6
: Port 11
: Programmable Clock
: Programmable Timer Output 0, 1
: Reset Input
: Serial Data Bus 0, 1
: Serial Clock
: Serial Input
: Serial Output
: Timer Input 0, 1
: Positive Power Supply
: Ground
: Main System Clock Oscillation 1, 2
: Subsystem Clock Oscillation 1, 2
6
Data Sheet U10165EJ2V0DS00
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