UPD750106(A) データシートの表示（PDF） - NEC => Renesas Technology

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UPD750106(A)

4 BIT SINGLE-CHIP MICROCONTROLLER

NEC => Renesas Technology 

µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Address 7 6 5

0 0 0 H MBE RBE 0

0 0 2 H MBE RBE 0

0 0 4 H MBE RBE 0

0 0 6 H MBE RBE 0

0 0 8 H MBE RBE 0

0 0 A H MBE RBE 0

0 0 C H MBE RBE 0

Figure 5-1. Program Memory Map (in µPD750104)

4

0 Internal reset start address

0

(high-order 4 bits)

Internal reset start address

(low-order 8 bits)

0 INTBT/INT4 start address (high-order 4 bits)

INTBT/INT4 start address (low-order 8 bits)

0 INT0

INT0

0 INT1

INT1

0 INTCSI

INTCSI

0 INTT0

INTT0

0 INTT1

INTT1

start address

start address

start address

start address

start address

start address

start address

start address

start address

start address

(high-order 4 bits)

(low-order 8 bits)

(high-order 4 bits)

(low-order 8 bits)

(high-order 4 bits)

CALLF

! faddr

instruction

entry

address

Branch address

of BR BCXA, BR

BCDE, BR !addr,

BRA !addr1Note or

CALLA !addr1Note

instruction

(low-order 8 bits)

(high-order 4 bits)

CALL !addr

instruction

subroutine entry

address

(low-order 8 bits)

(high-order 4 bits)

(low-order 8 bits)

BR $addr

instruction relative

branch address

-15 to -1,

+2 to +16

020H

07FH

080H

7FFH

800H

GETI instruction reference table

BRCB

!caddr

instruction

branch

address

Branch destination

address and

subroutine entry

address when

GETI instruction

is executed

FFFH

Note Can be used only in the Mk ΙΙ mode.

Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address

with only the 8 low-order bits of the PC changed.

17

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