UPD750106GBA データシートの表示（PDF） - NEC => Renesas Technology
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UPD750106GBA Datasheet PDF : 80 Pages
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µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
6. PERIPHERAL HARDWARE FUNCTIONS
6.1 Digital I/O Ports
The µPD750108 has the following three types of I/O port:
• 8 CMOS input pins (PORT0 and PORT1)
• 18 CMOS I/O pins (PORT2, PORT3, and PORT6 to PORT8)
• 8 N-ch open-drain I/O pins (PORT4 and PORT5)
Total: 34 pins
Table 6-1. Digital Ports and Their Features
Port name
Function
PORT0 4-bit input
PORT1
PORT2 4-bit I/O
PORT3
PORT4
PORT5
4-bit I/O (N-ch
open-drain can
withstand 13 V)
PORT6 4-bit I/O
PORT7
PORT8 2-bit I/O
Operation and feature
When the serial interface function is used, dual-function pins
function as output pins in some operation modes.
4-bit input port
Allows input or output mode setting in units of 4 bits.
Allows input or output mode setting in units of 1 bit.
Allows input or output mode setting in
units of 4 bits. Whether to use pull-up
resistors can be specified bit by bit with
the mask option.
Ports 4 and 5 can be
paired, allowing data
I/O in units of 8 bits.
Allows input or output mode setting in
units of 1 bit.
Allows input or output mode setting in
units of 4 bits.
Ports 6 and 7 can be
paired, allowing data
I/O in units of 8 bits.
Allows input or output mode setting in units of 2 bits.
Remarks
Also used as INT4, SCK,
SO/SB0, or SI/SB1.
Also used as INT0, INTI,
INT2 or TI0.
Also used as PTO0,
PTO1, PCL, or BUZ.
-
Also used as one of KR0
to KR3.
Also used as one of KR4
to KR7.
-
6.2 Clock Generator
The clock generator generates clocks which are supplied to the peripheral hardware in the CPU. Figure 6-1 shows
the configuration of the clock generator.
Operation of the clock generator is specified by the processor clock control register (PCC) and system clock control
register (SCC).
The main system clock and subsystem clock are used.
The instruction execution time can be made variable.
• 4, 8, 16, or 64 µs (when the main system clock is at 1.0 MHz)
• 2, 4, 8, or 32 µs (when the main system clock is at 2.0 MHz)
• 122 µs (when the subsystem clock is at 32.768 kHz)
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