µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Figure 6-1. Clock Generator Block Diagram
XT1
Subsystem
fXT
clock generator
XT2
CL1
Main system
fCC
clock generator
CL2 RC oscillation
Clock timer
• Basic interval timer (BT)
• Timer/event counter
• Timer counter
• Serial interface
• Clock timer
• INT0 noise eliminator
• Clock output circuit
1/1 to 1/4096
Frequency divider
1/2 1/4 1/16
WM.3
SCC
SCC3
SCC0
PCC
PCC0
PCC1
4
PCC2
HALTNote
PCC3
STOPNote
Oscillator
disable
signal
Selec-
tor
Selec-
tor
HALT flip-flop
S
RQ
Frequency
divider
1/4
Φ
• CPU
• INT0 noise
eliminator
•
Clock
output
circuit
PCC2, PCC3
clear signal
STOP flip-flop
QS
R
Wait release signal from BT
RESET signal
Standby release signal from
interrupt control circuit
Note Instruction execution
Remarks 1. fCC = Main system clock frequency
2. fXT = Subsystem clock frequency
3. Φ = CPU clock
4. PCC: Processor clock control register
5. SCC: System clock control register
6. One clock cycle (tCY) of the CPU clock (Φ) is equal to one machine cycle of an instruction.
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