µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
6.4 Clock Output Circuit
The clock output circuit outputs a clock pulse from the P22/PCL pin. This clock pulse is used for remote control
waveform output, peripheral LSIs, etc.
• Clock output (PCL): Φ, 125, 62.5, or 15.6 kHz (at 1.0 MHz)
Φ, 250, 125, or 31.3 kHz (at 2.0 MHz)
From the clock
generator
Φ
fCC/23
fCC/24
fCC/26
Figure 6-3. Clock Output Circuit Configuration
Selector
Output
buffer
PCL/P22
CLOM3 0 CLOM1 CLOM0 CLOM
PORT2.2
P22 output
latch
4
Internal bus
Bit 2 of PMGB
Port 2 input/
output mode
specification bit
Remark Measures are taken to prevent outputting a narrow pulse when selecting clock output enable/disable.
24