UPD750108CU(A) データシートの表示（PDF） - NEC => Renesas Technology

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UPD750108CU(A)

4 BIT SINGLE-CHIP MICROCONTROLLER

NEC => Renesas Technology 

µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

6.6 Clock Timer

The µPD750108 contains one channel for a clock timer. The clock timer provides the following functions:

• Sets the test flag (IRQW) with a 0.5 sec interval (when WM0 = 1).

• The standby mode can be released by IRQW.

• The 0.5 second interval can be generated from the subsystem clock (32.768 kHz).

• The time interval can be made 128 times faster by selecting the fast mode. This is convenient for program

debugging, testing, etc.

• Any of the frequencies (fW/24, fW/23, or fW can be output to the P23/BUZ pin. This can be used for beep and

system clock frequency trimming.

• The clock can be started from zero seconds by clearing the frequency divider.

From the

clock

generator

fCC Note

128

(7.8125 kHz)

fXT

(32.768 kHz)

Figure 6-5. Clock Timer Block Diagram

fw

27

fW

32.768 kHz

fw

or

214

Selector 7.8125 kHz

Frequency divider

fw

fw

23 24

Clear

Selector

INTW

IRQW

set signal

Selector

Output buffer

P23/BUZ

WM

WM7 0 WM5 WM4 WM3 WM2 WM1 WM0

PORT2.3

P23 output

latch

Bit 2 of PMGB

Port 2 input/

output mode

Bit test instruction

8

Internal bus

Note When a frequency-divided main system clock is used, 32.768 kHz cannot be selected as the source clock

frequency.

Remark The values in parentheses in the figure above are for fCC = 1.0 MHz, fXT = 32.768 kHz.

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