UPD75238GJ データシートの表示（PDF） - NEC => Renesas Technology

部品番号

コンポーネント説明

メーカー

UPD75238GJ

4 BIT SINGLE-CHIP MICROCOMPUTER

NEC => Renesas Technology 

CONTENTS

µPD75238

1. PIN FUNCTIONS ........................................................................................................................ 7

1.1 PORT PINS ...................................................................................................................................... 7

1.2 NON-PORT PINS ............................................................................................................................ 9

1.3 PIN INPUT/OUTPUT CIRCUITS .................................................................................................... 11

1.4 CONNECTION OF UNUSED µPD75238 PINS .............................................................................. 15

2. ARCHITECTURE AND MEMORY MAP OF THE µPD75238 ................................................... 16

2.1 DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES ................................ 16

2.2 GENERAL REGISTER BANK CONFIGURATION .......................................................................... 19

2.3 MEMORY-MAPPED I/O ................................................................................................................. 22

3. INTERNAL CPU FUNCTIONS .................................................................................................... 27

3.1 PROGRAM COUNTER (PC) ........................................................................................................... 27

3.2 PROGRAM MEMORY (ROM) ........................................................................................................ 27

3.3 DATA MEMORY (RAM) ................................................................................................................. 29

3.4 GENERAL REGISTERS ................................................................................................................... 31

3.5 ACCUMULATORS .......................................................................................................................... 32

3.6 STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS) ..................................... 32

3.7 PROGRAM STATUS WORD (PSW) .............................................................................................. 35

3.8 BANK SELECT REGISTER (BS) ..................................................................................................... 39

4. PERIPHERAL HARDWARE FUNCTIONS .................................................................................. 40

4.1 DIGITAL I/O PORTS ....................................................................................................................... 40

4.2 CLOCK GENERATOR ...................................................................................................................... 49

4.3 CLOCK OUTPUT CIRCUIT ............................................................................................................. 58

4.4 BASIC INTERVAL TIMER ............................................................................................................... 61

4.5 TIMER/EVENT COUNTER ............................................................................................................. 63

4.6 CLOCK TIMER ................................................................................................................................. 69

4.7 TIMER/PULSE GENERATOR ......................................................................................................... 71

4.8 EVENT COUNTER .......................................................................................................................... 77

4.9 SERIAL INTERFACE ....................................................................................................................... 79

4.10 A/D CONVERTER ........................................................................................................................... 113

4.11 BIT SEQUENTIAL BUFFER ............................................................................................................ 119

4.12 FIP CONTROLLER/DRIVER ............................................................................................................ 119

5. INTERRUPT FUNCTION ............................................................................................................ 131

5.1 CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT .................................................... 131

5.2 HARDWARE OF THE INTERRUPT CONTROL CIRCUIT .............................................................. 133

5.3 INTERRUPT SEQUENCE ................................................................................................................ 138

5.4 MULTIPLE INTERRUPT PROCESSING CONTROL ...................................................................... 139

5.5 VECTOR ADDRESS SHARE INTERRUPT PROCESSING ............................................................ 141

5

Share Link: