UPD75212ACW データシートの表示（PDF） - NEC => Renesas Technology

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UPD75212ACW

4-BIT SINGLE-CHIP MICROCOMPUTER

NEC => Renesas Technology 

µPD75212A

DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40

to +85 °C)

PARAMETER

Data retention power

supply voltage

Data retention power

supply current *1

Release signal set time

Oscillation stabilization

wait time *2

SYMBOL

VDDDR

IDDDR

tSREL

tWAIT

TEST CONDITIONS

VDDDR = 2.0V

Release by RESET

Release by interrupt request

MIN. TYP. MAX. UNIT

2.0

6.0

V

0.1

10

µA

0

µs

217/fX

ms

*3

ms

* 1. Current to the on-chip pull-down resistor and power-on reset circuit (mask option) is not included.

2. Oscillation stabilization wait time is time to stop CPU operation to prevent unstable operation upon oscillation

start.

3. According to the setting of the basic interval timer mode register (BTM) (see below).

BTM3

—

—

—

—

BTM2

0

0

1

1

BTM1

0

1

0

1

BTM0

0

1

1

1

Wait Time (Values at fXX = 4.19 MHz in parentheses)

220/fXX (approx. 250 ms)

217/fXX (approx. 31.3 ms)

215/fXX (approx. 7.82 ms)

213/fXX (approx. 1.95 ms)

Data Retention Timing (STOP Mode Release by RESET)

Internal Reset Operation

HALT Mode

STOP Mode

Operating Mode

VDD

STOP Instruction Execution

RESET

Data Retention Mode

VDDDR

tSREL

tWAIT

57

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