UPD78044F データシートの表示（PDF） - NEC => Renesas Technology
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UPD78044F Datasheet PDF : 72 Pages
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mPD78042F, 78043F, 78044F, 78045F
FUNCTIONAL OUTLINE
Item
Product name
mPD78042F
mPD78043F
mPD78044F
Internal
memory
ROM
Internal high-speed RAM
16K bytes
512 bytes
24K bytes
32K bytes
1024 bytes
Buffer RAM
64 bytes
FIP display RAM
48 bytes
General registers
8 bits ¥ 32 registers (8 bits ¥ 8 registers ¥ 4 banks)
Instruction
cycle
For main system clock
For subsystem clock
Instruction set
I/O ports (including those
multiplexed with FIP pins)
Variable instruction execution time
0.4 ms/0.8 ms/1.6 ms/3.2 ms/6.4 ms (at 5.0 MHz)
122 ms (at 32.768 kHz)
• Multiplication/division (8 bits ¥ 8 bits, 16 bits ÷ 8 bits)
• Bit (set, reset, test, Boolean algebra)
Total
• CMOS input
• CMOS I/O
• N-ch open-drain
• P-ch open-drain I/O
• P-ch open-drain output
: 68 lines
: 2 lines
: 27 lines
: 5 lines
: 16 lines
: 18 lines
mPD78045F
40K bytes
FIP controller/driver
A/D converter
5
Serial interface
Timer
Total
: 34 lines
• Segments : 9 to 24 lines
• Digits
: 2 to 16 lines
• 8-bit resolution ¥ 8 channels
• Power supply voltage: AVDD = 4.0 to 5.5 V
• 3-wire serial I/O/SBI/2-wire serial I/O selectable modes: 1 channel
• 3-wire serial I/O mode (with automatic transmission/
reception function of up to 64 bytes)
: 1 channel
• 16-bit timer/event counter
• 8-bit timer/event counter
• Watch timer
• Watchdog timer
• 6 bit up/down counter
: 1 channel
: 2 channels
: 1 channel
: 1 channel
: 1 channel
Timer output
Clock output
3 lines (one for 14-bit PWM output)
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz
(Main system clock: at 5.0 MHz)
32.768 kHz (Subsystem clock: at 32.768 kHz)
Buzzer output
1.2 kHz, 2.4 kHz, 4.9 kHz (Main system clock: at 5.0 MHz)
Vectored
interrupt
Maskable interrupt
Non-maskable interrupt
Internal 10 lines, external 4 lines
Internal 1 line
Software interrupt
1 line
Text input
Internal 1 line
5
Power supply voltage
VDD = 2.7 to 5.5 V
Package
80-pin plastic QFP (14 ¥ 20 mm)
4
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