UPSD3233 データシートの表示（PDF） - STMicroelectronics

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UPSD3233

Flash Programmable System Devices with 8032 Microcontroller Core and 64 Kbit SRAM

STMicroelectronics 

uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV

Figure 79. Synchronous Clock Mode Timing – PLD

tCH

tCL

CLKIN

INPUT

REGISTERED

OUTPUT

tS

tH

tCO

AI02860

Table 128. CPLD Macrocell Synchronous Clock Mode Timing (5V Devices)

Symbol

Parameter

Conditions

Min

Max

PT

Aloc

Turbo Slew

Off rate(1)

Unit

Maximum Frequency

External Feedback

1/(tS+tCO)

40.0

MHz

fMAX

Maximum Frequency

Internal Feedback (fCNT)

1/(tS+tCO–10)

66.6

MHz

Maximum Frequency

Pipelined Data

1/(tCH+tCL)

83.3

MHz

tS

Input Setup Time

12

+ 2 + 10

ns

tH

Input Hold Time

0

ns

tCH

Clock High Time

Clock Input

6

ns

tCL

Clock Low Time

Clock Input

6

ns

tCO

Clock to Output Delay

Clock Input

13

– 2 ns

tARD

CPLD Array Delay

Any macrocell

11

+2

ns

tMIN

Minimum Clock Period(2)

tCH+tCL

12

ns

Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.

2. CLKIN (PD1) tCLCL = tCH + tCL.

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