UPSD3233 データシートの表示（PDF） - STMicroelectronics
部品番号
コンポーネント説明
メーカー
UPSD3233
STMicroelectronics
UPSD3233 Datasheet PDF : 170 Pages
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uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Figure 82. Input Macrocell Timing (product term clock)
tINH
tINL
PT CLOCK
tIS
tIH
INPUT
OUTPUT
AI03101
tINO
Table 132. Input Macrocell Timing (5V Devices)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Unit
tIS
Input Setup Time
(Note 1)
0
ns
tIH
Input Hold Time
(Note 1)
15
+ 10 ns
tINH
NIB Input High Time
(Note 1)
9
ns
tINL
NIB Input Low Time
(Note 1)
9
ns
tINO
NIB Input to Combinatorial Delay
(Note 1)
34
+ 2 + 10 ns
Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to tAVLX and tLXAX.
Table 133. Input Macrocell Timing (3V Devices)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Unit
tIS
Input Setup Time
(Note 1)
0
ns
tIH
Input Hold Time
(Note 1)
25
+ 20 ns
tINH
NIB Input High Time
(Note 1)
12
ns
tINL
NIB Input Low Time
(Note 1)
12
ns
tINO
NIB Input to Combinatorial Delay
(Note 1)
46
+ 4 + 20 ns
Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX.
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