V29LC51002-90J データシートの表示（PDF） - Mosel Vitelic Corporation

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V29LC51002-90J

2 MEGABIT (262,144 x 8 BIT) 5 VOLT CMOS FLASH MEMORY

Mosel Vitelic Corporation  

MOSEL VITELIC

V29LC51002

Table 2. Command Codes

Command

Sequence

First Bus

Second Bus

Third Bus

Fourth Bus

Program Cycle Program Cycle Program Cycle Program Cycle

Address Data Address Data Address Data Address Data

Fifth Bus

Six Bus

Program Cycle Program Cycle

Address Data Address Data

Read

XXXXH F0H

Read

5555H AAH 2AAAH 55H 5555H F0H RA(1)

RD(2)

Autoselect 5555H AAH 2AAAH 55H 5555H 90H 00H

40H(6)

01H

82H(7)

Byte

Program

5555H AAH 2AAAH 55H 5555H A0H PA

PD(4)

Chip Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Sector Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA(5)

30H

NOTES:

1. RA: Read Address

2. RD: Read Data

3. PA: The address of the memory location to be programmed.

4. PD: The data at the byte address to be programmed.

5. SA(5): Sector Address

6. 40H: Manufacturing ID

7. 82H: Device ID

Chip Erase Cycle

The V29LC51002 features a chip-erase

operation. The chip erase operation is initiated by

using a specific six-bus-cycle sequence: two unlock

program cycles, a setup command, two additional

unlock program cycles, and the chip erase

command (see Table 2).

The automatic erase begins on the rising edge of

the last WE or CE pulse in the command sequence

and is completed in 3 sec max.

V29LC51002 Rev. 0.5 October 2000

9

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