VP2612CGGPFR データシートの表示（PDF） - Mitel Networks

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VP2612CGGPFR

Video Multiplexer

Mitel Networks 

VP2612

PIN DESCRIPTIONS

DBUS7:0 The input data bus from VP2611. The data type is

defined by the value present on DMODE3:0

DMODE3:0 These inputs define the data type present on the

data bus D7:0. Polarities are given in Table 1.

DCLK A strobe for DM3:0 and DBUS7:0.The high

going edge latches data into the VMUX.

HD7:0 A bidirectional tri-state data bus connecting the

VMUX to the system processor.

HA3:0 Four system processor address bits used to

address internal registers.

WR

An active low write strobe from the system

processor.

RD

An active low read strobe from the system

processor.

CEN

An active low chip select input from the system

processor.

OVR

An active high output which signals impending

buffer overflow.

STUFF An active high output that signals that FEC stuffing

is occuring.

MTICK An output which pulses high for every macroblock

received.

TOOM

This active high output indicates that the picture is

likely to exceed the allowable number of bits per

picture.

VAL

This line is taken low to indicate that the VMUX is

ready to transmit valid data. The C line in an

X21 system.

TD

This is the serial data output from the VMUX.

CTS

Indicates that the receiver can accept data. The I

line in an X21 system.

RDY

Indicates that the receiver can accept data. The

R line in an X21 system.

XCLK X21 line clock input. 0 to 2.048MHz.

SCLK System clock input. Only the high going edge is

used internally, apart from TXWE generation.

FS

A 29.97 Hz frame strobe for the temporal reference

counter. Must be high for at least 4 SCLK periods.

RES

Active low reset signal. Must be low for at least 16

SCLK periods.

TXA14:0 Address output to Transmission buffer.

TXD7:0 Bidirectional data interface to Transmission buffer.

TXE1 Active low chip enable for the Transmission buffer.

If a 256kBit buffer is being used this Chip Enable

should be used.

TXE2

Active low chip enable for the Transmission buffer.

This is used for the optional second memory chip,

if a 512kBit buffer is being used.

TXWE

TXOE

Active low write enable for the Transmission buffer.

Active low O/P enable for the Transmission buffer.

TCK

TMS

TDI

Test clock for JTAG.

Test mode select.

Test data I/P.

TDO

TRST

Test data O/P.

JTAG reset.

TOE

When low ALL O/P pins are high impedance.

NOTE: "Barred" active low signals do not appear with a

bar in the main body of the text.

OPERATIONS OF MAJOR BLOCKS

Variable Length Coding

This block is responsible for ordering the data from the

VP2611 Encoder into the correct sequence for the H261 bit

stream, and for performing the variable length coding. It also

uses data supplied by the system controller and the Temporal

Reference Counter.

Data for PTYPE, PSPARE, GSPARE is only obtained

from the system controller, and only 8 bits of PSPARE and

GSPARE information can be transmitted per picture or GOB

respectively. The temporal reference can either be obtained

from an internal counter, from the VP2611 outputs, or can be

written by the system controller. The actual source is

determined by bits in a control register as described later. The

internal counter is clocked from either a frame clock with a

maximum frequency of 29.97Hz, or a 29.97Hz clock derived

from the 27MHz system clock, or it simply counts H.261

frames from the encoder.

There is no support provided for macroblock stuffing,

however FEC stuffing is implemented, and can be used to

provide bit stuffing.

This block is also responsible for converting the absolute

values that are output from the V2611 into the relative values

that are required in parts of the H261 bitstream. The VMUX

has been designed so that it can accept ±15 motion vectors,

rather than the +7/-8 motion vectors produced by the VP2611.

Thus it will be compatible with any future upgrades to the

VP2611 that increase the size of the motion estimator search

window.

VMUX Block

The VMUX section performs the bit packing on the data

coming from the variable length coder. This data is in the form

of a delimiter and a variable number of valid bits. The VMUX

section packs these variable length fields into bytes for

storage in the transmission buffer.

The transmission buffer is controlled by this block. It thus

generates read and write pointers, and performs the

arbitration between read and write operations. Buffer level

2

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