VP2612CGGPFR データシートの表示（PDF） - Mitel Networks

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VP2612CGGPFR

Video Multiplexer

Mitel Networks 

VP2612

Address

Function

Read / Write

0

PTYPE

W

1

Temporal Reference

W

2

PSPARE

W

3

TR Source

W

4

GSPARE

W

5

Not Used

6

Not Used

7

Not Used

8

TX-buffer Write Address MSB

R

9

TX-buffer Write Address LSB*

R

A

TX-buffer Read Address MSB

R

B

TX-buffer Read Address LSB*

R

C

FEC / VMUX status word

W

D

Bits per Picture Threshold

W

E

Not Used

F

Not Used

* N.B. The LSB must be read after the appropriate MSB.

Table 2. Address Locations

PTYPE This is the picture type as defined in H261.

The bits are assigned as follows:

Bit 0

Split screen indicator, "0" off, "1" on.

Bit 1

Document camera indicator, "0" off, "1" on.

Bit 2

Freeze picture release, "0" off, "1" on.

Bit 3

Source Format, "0" QCIF, "1" CIF.

Bit 4:5 Both are set to one as presently defined in the

H261 specification

[Bit 0 is LSB].

These values can be changed at will by the system processor,

and will be transmitted at the start of each picture.

ADDRESS

CHIP

SELECT

READ

STROBE

DATA

OUT

READ CYCLE

Tas Tah

Trs

Tac

Tlz

Tsh

Tri

Thz

Data Valid

Temporal Reference If the temporal reference is being

written from the system processor, then the 5 LSB's in this

register are used to define the next temporal reference value

to be transmitted.

PSPARE This register holds 8 bits of PSPARE information

which may be transmitted for each picture. The data in the

PSPARE register will be transmitted at the start of the next

picture after it has been written. Once an item of data has been

transmitted, it will not be re-transmitted until data is written

from the system processor. It is the responsibility of the

system processor to ensure that it does not rewrite to this

register before the previous value has been transmitted. This

can be done by utilizing a frame interrupt from the video source

in conjunction with the MBTICK output from the VMUX.

TR Source The 3 LSB's in this register define the source for

the strobe used by the 5 bit temporal reference counter. When

the sytem processor is selected, the counter value is replaced

by the contents of the Temporal Reference Register.

VALUE

SOURCE

0XX

System Processor

100

Actual coded frames from the VP2611

are counted

101

SCLK is divided down to provide a

29.97 Hz frame strobe

110

The strobe is provided by the frame

strobe input pin (FS)

111

Illegal

GSPARE This register holds 8 bits of GSPARE information

which may be transmitted every GOB. Once written the data

is transmitted at the start of the next GOB, but will not be re-

transmitted until the system processor again writes to this

address. The system processor must ensure that data is not

overwritten before it is used.

TX Buffer Addresses

These allow the system

processor to monitor the level of the buffer. The write pointer

should be read first to minimize the error between the the two

ADDRESS

CHIP

SELECT

WRITE

STROBE

DATA

IN

WRITE CYCLE

Tas Tah

Tws

Tsh

Twi

Twa

Tds

Tdh

Data Valid

CHARACTERISTIC

SYMBOL MIN

Addresss Set Up Time Tas

Address Hold Time

Tah

Cip Select Set Up Time Trs

Chip Select Hold Time Tsh

Strobe In active Time Tri

Data Access Time

Tac

Delay to O/P's low Z

Tlz

Delay to O/P's high Z Thz

10ns

10ns

10ns

2ns

Øns

4Øns

MAX

10 +5Øns

25ns

25ns

NOTE

Ø is the period of the

input clock

CHARACTERISTIC

SYMBOL

Addresss Set Up Time

Tas

Address Hold Time

Tah

Chip Select Set Up Time Tws

Chip Select Hold Time

Tsh

Strobe In active Time

Twi

Strobe Active Time

Twa

Data Set Up Time

Tds

Data Hold Time

Tdh

MIN

10ns

10ns

10ns

2ns

2Øns

2Øns

10ns

10ns

MAX

Figure 4. Host Controller Timing

5

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