VP2612CGGPFR データシートの表示（PDF） - Mitel Networks

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VP2612CGGPFR

Video Multiplexer

Mitel Networks 

VP2612

XCLK

VAL

TD

CTS

RDY

Line rate clock

Ready to send

Transmitted Data

Clear To Send

Receiver ready

Of these signals XCLK, CTS and RDY are supplied by

the receiving device, the latter two indicating that the receiver

is ready to accept data. The VAL line is used to signal that the

VMUX is ready to start transmitting valid data, and the TD line

provides the data. The signaling convention is as follows:

CTS = 1

RDY = 0

Receiving device not ready

CTS = 0

RDY = X

Receiving device ready to accept data

CTS =1

RDY =1

Receiving device ready to accept data

The VAL line is taken high by the reset input, and when

the receiving device signals that it is ready to accept data then

the VP2612 takes the VAL line low on a falling edge of an

XCLK. The data is then clocked out on subsequent falling

edges of the XCLK signal, so that it can be sampled by the

receiver on the rising edge of the clock.

If a simple serial interface is required, the CTS input

should be tied low and the RDY input tied high. It is possible

to use a variable rate clock provided the maximum

instantaneous bit rate does not exceed 8Mbits/s, and the

average clock rate over 32 bits does not exceed 2Mbits/s.

Timing delays with respect to the incoming XCLK are shown

in Figure 6.

JTAG Test Interface

The VP2612 includes a test interface consisting of a

boundary scan loop of test registers placed between the pads

and the core of the chip. The control of this loop is fully JTAG/

IEEE 1149-1 1990 compatible. Please refer to this document

for a full description of the standard.

The interface has five dedicated pins: TMS, TDI, TDO,

TCK and TRST. The TRST pin is an independent reset for the

interface controller and should be pulsed low, soon after

power up; if the JTAG interface is not to be used it can be tied

low permanently. The TDI pin is the input for shifting in serial

instruction and test data; TDO the output for test data. The

TCK pin is the independent clock for the test interface and

registers, and TMS the mode select signal.

TDI and TMS are clocked in on the rising edge of TCK,

and all output transitions on TDO happen on its falling edge.

Instructions are clocked into the 3 bit instruction register

(no parity bit) and the following instructions are available.

Instruction Register

( MSB first )

Name

111

BYPASS

000

EXTEST

010

SAMPLE/PRELOAD

XCLK

I/P

READY FROM

RECEIVER

DATA VALID

O/P (VAL)

DATA

O/P

20 min

RECEIVER READY R =1, I =1

25ns max

25ns max

25ns max

DATA VALID

Figure 6. Serial Interface Timing

The TAP controller used in this device does not support

a separate INTEST instruction but allows EXTEST to drive the

internals of the device as well as to drive the output pins.

Output enables are thus present in the chain which are not

connected to pins but which allow EXTEST to be used to

control the impedance of all the outputs. The JTAG signal

TXD controls the TXD bus, HD controls the HD bus, and TOPS

controls all remaining outputs. The TOE pin, which can

separately be used to control the impedance of all the outputs,

can be monitored as an input through the scan chain but

cannot be used to control the outputs through the TAP

controller.

7

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