VP2614 データシートの表示（PDF） - Mitel Networks
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VP2614 Datasheet PDF : 12 Pages
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VP2614
SCLK
ADDRESS
O/P
CHIP ENABLE/
O/P ENEBALE
20ns
max
DATA I/P
ADDRESS
O/P
CHIP
ENABLE
20ns max
DATA
O/P
WRITE
ENABLE
ADDRESS VALID
0ns
10ns min
min
Tac
VALID
READ CYCLE
WRITE CYCLE
20ns
max
DATA VALID
20ns
max
20ns
max
Fig 3 : External Buffer Timing
Not all this side information is used by the VP2615 De-
coder, but is still made available on the data output bus
DBUS7:0. This is described in the section on Additional
Information. In addition the side information can be examined
by the system controller.
Requirements for the complete decoder system are such
that it is desirable for the VP2614 /15 pair to free run, and to
ignore the Temporal References embedded in the video
bitstream. The pair then always process the bitstream, when-
ever code bits are available, using the processing rate needed
for the full 30 Hz frame rate. Operating in this manner allows
the de-mux core to be closely coupled to the VP2615 Interface
circuitry, and no additional buffering is necessary. The de-
multiplexing process is then locked to the macroblock timing
structure needed by the VP2615.
LINE INTERFACE
Bitstream inputs to the device are controlled by an asyn-
chronous line input strobe, which when data is valid is enabled
by a Data Valid signal. Detailed timing information is given in
Figure 2.
Maximum input frequency is 4 MHz and the rising edge of
the strobe is used to internally latch the data. The VP2614
generates a Ready signal which goes invalid when data
cannot be accepted. This, for example, occurs during system
reset or if the Received Data Buffer overflows.
EXTERNAL BUFFER REQUIREMENTS
The external buffer must be a 32K x 8 bit static RAM, and
must comply with the timing requirements given in Figure 3.
Under normal operating conditions the buffer will not overflow,
however it is conceivable that under some unforseen condi-
tion the buffer may fill and then overflow. For this reason a
Buffer Full Flag is provided in one of the Status Registers. This
is asserted when the buffer is 90% full, and is not itself an error
condition. If the buffer continues to fill and eventually over-
flows, then the Ready Signal to the line interface goes invalid.
The effect of overflow is to also clear the buffer and the Buffer
Empty Flag will be raised. There is no status bit to indicate
overflow, but an extended period of Buffer Full followed by
Buffer Empty can be used to infer the condition.
4
DMODE3:0
FUNCTION
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
GOB Number
MB Number
Control Decisions
Quant Value
Horizontal MV
Vertical MV
Coded Blk Pattern
Sub-Block No
Zero Run Count
RLC Coefficient
Not used
Not used
Not used
Not used
Not used
Wait State
Table 1. Output Codes
VP2615 INTERFACE
The VP2614 provides a glueless interface to the VP2615
Decoder. Run length coded coefficients and control informa-
tion are transmitted over the DBUS7:0 bus, and are identified
by the code on the DMODE3:0 bus given in Table 1. The
VP2614 produces a continuous DCLK which is used to strobe
data into the VP2615. This is derived by dividing the system
clock by two, and when no data is actually available the
DMODE3:0 bus will indicate a wait state. Timing is shown in
Figure 4.
The VP2615 expects a macroblock and its control infor-
mation to be transferred over a minimum period, nominally
equivalent to 2048 system clock cycles but with allowance for
the asynchronous DCLK. Wait states are thus inserted as
necessary by the VP2614 in order to enforce this macroblock
period. Under normal circumstances the VP2614 will not take
longer than 2048 clock periods to produce a macroblock, but
some 10% extra time is available for each macroblock before
the 30 Hz frame rate becomes impossible to maintain.
The start of a macroblock transfer is identified by the
presence of the Control Decisions Byte ( DMODE3:0 = 0010).
Each macroblock slot must at least consist of this Control
Decisions Byte, followed by the GOB number and then the
Macroblock number. No further bytes are mandatory.
When high, Bit 0 in the Control Decisions Byte indicates a
Fixed Macroblock, and a high on Bit 1 indicates Inter Mode
coding. A high on Bit 2 indicates that the macroblock was
filtered, and a high on Bit 3 indicates that Motion Compensa-
SCLK
DCLK
O/P
DATA FROM
VP2614
25ns max
25ns max
DATA VALID
25ns max
DMODE
3:0
DATA VALID
Fig 4 : Output Timing
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