VP2614 データシートの表示（PDF） - Mitel Networks
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VP2614 Datasheet PDF : 12 Pages
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VP2614
tion was used. When Bit 7 is high this indicates that CIF
resolution is in use, but the VP2615 does not use this informa-
tion. Instead the host controller must supply this information.
The VP2615 is essentially a Macroblock Processor which
produces decoded data for the position on the screen defined
by the GOB and Macroblock number. Since the H.261 speci-
fication allows macroblocks to be skipped, then the VP2614
generates dummy Fixed Macroblocks if necessary ( see
below ) which are still separated by 2048 clock cycles.
Similarly after Video lock has been re-gained the VP2614 will
generate Fixed Macroblocks for those missing in the se-
quence, even if this wraps around into the next picture.
These steps ensure that a complete picture, containing
dummy data when necessary, is always supplied by the
VP2614. The Fixed Macroblock bit in the Control Decisions
Byte is set when dummy data is needed, and Intra Mode
decoding is specified. This causes the VP2615 to output
macroblock data from the previously decoded picture, which
was already in the frame store.
ADDITIONAL INFORMATION
Picture Type, PSPARE and GSPARE information is not
used by the VP2615 decoder. In future or proprietary uses of
H.261 this information could become considerable and be
useful to other devices in the system. This can conveniently be
supplied by using the DBUS7:0 bus when the DMODE3:0 bus
indicates that a wait state is present and there is no useful
information for the VP2615. An additional control bus PM2:0
defines the additional information that is present, with the
coding given below:
PM2:0
000
001
010
011
100
111
ADDITIONAL PARAMETER
Temporal Reference
GSPARE transfer
PSPARE transfer
PTYPE transfer
Quantizer step value
Data present is that defined by DMODE3:0
SYSTEM CONTROLLER INTERFACE
A conventional microprocessor interface is used consist-
ing of a byte wide bi-directional data bus, four address bits, a
chip enable and separate read and write strobes. Detailed
timing is given in Figure 5.
In addition two outputs are available which can be used as
interrupts if necessary. These can be disabled by control bits.
When the Error Interrupt Source Bit is set, the ERROR signal
indicates that an error has occurred in the FEC frame align-
ment module. The Frame Lock Lost Status Bit is also set. The
output signal is cleared by reading the status register and will
be set again when frame alignment is again achieved. If the
host has forced a loss of alignment then ERROR does not go
active when lock is lost, but it will still go active when lock is re-
gained.
When the Error Interrupt Source Bit is cleared, then the
ERR output also goes active when Video Lock is lost. Reading
the Status Register will detemine the actual cause of the ERR
interrupt.
The EVT signal allows the controller to synchronize with
picture related parameters extracted from the bitstream. It
goes active when new picture status data is available, as does
the Picture Ready bit in Status Register A. This bit and the
output signal are cleared when any Status Register is read.
The pipeline delay of two macroblock periods through the
VP2615 decoder will give the controller time to react to
changes in PTYPE affecting the final output of the picture in
question. When PTYPE specifies a change between CIF and
QCIF, the controller has an amount of time equivalent to that
needed to decode the first GOB before it needs inform the
VP2615 of the change in operation.
The addresses and functions of the various control and
status registers are given below. Setting a Control Bit always
performs the function specified, and a high in a Status Regis-
ter indicates the state is true. All error counters saturate at their
maximum values, and are prevented from changing whilst
being read.
ADDRESS
CHIP
SELECT
READ
STROBE
DATA
OUT
READ CYCLE
Tas Tah
Trs
Tac
Tlz
Tsh
Tri
Thz
Data Valid
ADDRESS
CHIP
SELECT
WRITE
STROBE
DATA
IN
WRITE CYCLE
Tas Tah
Tws
Tsh
Twi
Twa
Tds
Tdh
Data Valid
CHARACTERISTIC
SYMBOL MIN
Addresss Set Up Time Tas
Address Hold Time
Tah
Cip Select Set Up Time Trs
Chip Select Hold Time Tsh
Strobe In active Time Tri
Data Access Time
Tac
Delay to O/P's low Z
Tlz
Delay to O/P's high Z Thz
10ns
10ns
10ns
2ns
Øns
6Øns
MAX
10 +7Øns
25ns
25ns
NOTE
Ø is the period of the
input clock
CHARACTERISTIC
SYMBOL
Addresss Set Up Time
Tas
Address Hold Time
Tah
Chip Select Set Up Time Tws
Chip Select Hold Time
Tsh
Strobe In active Time
Twi
Strobe Active Time
Twa
Data Set Up Time
Tds
Data Hold Time
Tdh
MIN
10ns
10ns
10ns
2ns
3Øns
2Øns
10ns
10ns
MAX
Fig 5 : Host Controller Timing
5
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