VP2615 データシートの表示（PDF） - Mitel Networks

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VP2615

H.261 Decoder

Mitel Networks 

VP2615

OPERATION OF MAJOR BLOCKS

Run Length Decode

This block converts the run length coded data into 64

individual coefficient values, inserting zero value coefficients

where required. It then re-orders these 8 bit quantized DCT

coefficients from the zig zag arrangement into normal 8 x 8

format.

Inverse Quantise

This circuit reconstructs the 12 bit DCT coefficients from

the 8 bit quantized coefficients using the 5 bit Quantization

Value. This is performed using the following formulae.

If QUANT is odd :

REC = QUANT*(2*LEVEL+1) : LEVEL > 0

REC = QUANT*(2*LEVEL-1) : LEVEL < 0

If QUANT is even :

REC = QUANT*(2*LEVEL+1)-1 : LEVEL > 0

REC = QUANT*(2*LEVEL-1)+1 : LEVEL < 0

For Intra coded DC coefficients :

REC = 8*LEVEL

except if LEVEL=255 when REC=1024

If LEVEL=0 then REC=0 in all cases.

The reconstructed values (REC) are passed through a

clipping circuit in case of arithmetic overflow.

Inverse DCT

This circuit performs an Inverse Discrete Cosine Trans-

form on an 8x8 block of 12 bit coefficients outputting 9 bit

signed pixel data. This IDCT fully meets the CCITT specifica-

tion.

Frame Store Interface

The whole of the previous picture is stored in either two

external 64K x 16 DRAMs, or in a single 256 k x 16 DRAM, or

in four 256K x 4 DRAM's. A bit in the user defined Input Set Up

Data determines whether 64K or 256K DRAM's are to be

used. In the latter case, use OE1 as ADR8, RW1 as R/W and

do not connect RW2 and OE2.Table 1 specifies the worst case

maximum and minimum times which must be achieved by the

DRAM for correct operation with the VP2615. Times in the

DRAM specification must be less than or equal to the times

stated.

The Frame Store Interface manages all read and write

operations to these DRAM's. During the course of each

MacroBlock, the "Best Fit" MacroBlock is read from the

DRAMs and the fully processed MacroBlock is written back. In

this way, the previous frame is continually updated. The

DRAM controller also takes care of refresh for the DRAMs.

Figure 3 illustrates the effects of the pipeline delays

through the device; whilst macro block 3 is being input the

previous macroblock (2) is being decoded and needs the

equivalent macroblock from the previous frame to be read

from the frame store. At the same time macroblock 1, which

has already been decoded, is being written to the frame store

DIN Input

Frame Store Read

Frame Store Write

YUV Output

Minimum of

2048 cycles

MB3

MB4

MB5

MB6

MB2

MB3

MB4

MB5

MB1

MB2

MB3

MB4

MB1

MB2

MB3

MB4

Fig 3 : MacroBlock Pipelining

SYMBOL

PARAMETER

MINIMUM

MAXIMUM

t RAC

t CAC

t RP

t CP

t RAS

t CAS

t REF

Access time from RAS

Access time from CAS

RAS precharge time

CAS precharge time

RAS pulse width

CAS pulse width

Time to refresh 256 rows

-

-

50ns or under

15ns or under

90ns or under

50ns or under

-

105ns or under

25ns or under

-

-

-

-

0.25ms or over

N.B. All times are quoted assuming 27MHz operation. For lower clock

frequencies increase the above values proportionately.

Table 1. External DRAM Timing Requirements

3

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