VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC7139
Quad Transceiver for
Gigabit Ethernet and Fibre Channel
RCx0
RCM=LOW
RCx1
Figure 4: Receive Timing Waveforms
RCx0
RCM=HIGH
RCx1
Rx(0:9)
SYNCx
VALID
T1
T2
VALID
VALID
+/-Rx
RCx1
Rx0 Rx1 Rx2
RLAT
Table 4: Receive AC Characteristics
Parameters
Description
Min Typ Max Units
Conditions
T1
T2
T3
T4
TR, TF
RLAT
TLOCK
TTL Outputs Valid prior to RCx1/
RCx0 rise
4.0
3.0
TBD
—
—
—
—
@ 1.0625Gb/s
—
ns @ 1.25Gb/s
—
@ 1.36Gb/s
TTL Outputs Valid after RCx1 or
RCx0 rise
3.0
2.0
TBD
—
—
—
—
@ 1.0625Gb/s
—
ns @ 1.25Gb/s
—
@ 1.36Gb/s
Delay between rising edge of RCx1 10 x TRX
to rising edge of RCx0
-500
—
10 x TRX
+500
ps
TRX is the bit period of the
incoming data on Rx.
Period of RCx1 and RCx0
1.98 x
TREF
—
2.02 x
TREF
ps
Whether or not locked to
serial data.
TTL Output rise and fall time
—
—
2.4
ns
Between VIL(max) and
VIH(min), into 10 pf. load.
Latency from serial bit Rx0 to rising 12bc +
edge RCx1
2.77ns
—
13bc +
7.28ns
bc = Bit clock
ns = Nano second
Data acquisition lock time(1)
—
—
1400
bit 8B/10B IDLE pattern.
times Tested on a sample basis
NOTE: (1) Probability of recovery for data acquisition is 95% per Section 5.3 of FC-PH, rev. 4.3.
G52196-0, Rev 3.3
5/14/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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