VSC8111QB データシートの表示（PDF） - Vitesse Semiconductor

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VSC8111QB

ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation

Vitesse Semiconductor 

Data Sheet

VSC8111

VITESSE

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 155/622 Mb/s Transceiver

Mux/Demux with Integrated Clock Generation

TXCLKOUT-

TXCLKOUT+

TXDATAOUT+

TXDATAOUT-

Figure 10: Transmit High Speed Data Timing Diagram

TTXCLK

TSKEW TSKEW

Table 10: Transmit High Speed Data Timing Table (STS-12 Operation)

Parameter

Description

Min

TTXCLK

Transmit clock period

-

TSKEW

Skew between the falling edge of TXCLKOUT+ and

valid data on TXDATAOUT

-

Typ

1.608

-

Max

-

250

Units

ns

ps

Table 11: Transmit High Speed Data Timing Table (STS-3 Operation)

Parameter

TTXCLK

TSKEW

Description

Transmit clock period

Skew between the falling edge of TXCLKOUT+ and

valid data on TXDATAOUT

Min

Typ

Max

Units

-

6.43

-

ns

-

-

250

ps

Data Latency

The VSC8111 contains several operating modes, each of which exercise different logic paths through the

part. Table 12 bounds the data latency through each path with an associated clock signal.

Table 12: Data Latency

Circuit Mode

Description

Transmit

Receive

Equipment

Loopback

Facilities

Loopback

Data TXIN [7:0] to MSB at TXDATAOUT

MSB at RXDATAIN to data on RXOUT [7:0]

Byte data TXIN [7:0] to byte data on RXOUT [7:0]

MSB at RXDATAIN to MSB at TXDATAOUT

Clock

Reference

TXCLKOUT

RXCLKIN

TXCLKOUT

RXCLKIN

Range of

Clock cycles

4-13

24-32

27-35

2

G52142-0, Rev 4.2

8/31/98

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741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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