VSC8151 データシートの表示（PDF） - Vitesse Semiconductor
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VSC8151 Datasheet PDF : 30 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
2.488Gb/s SONET/SDH
STS-48/STM-16 Section Terminator
Advance Product Information
VSC8151
Line Overhead Modification
It is understood that the ability to modify a portion of the line overhead is not permitted in a section termi-
nation function. The ability to do so has been included in order to leave such decisions at the users discretion.
Scrambler
The outgoing data bytes are scrambled with a generating polynomial of 1 + X6 + X7 and sequence length of
127, prior to being multiplexed and output as a serial signal. The A1, A2, and J0/Z0 bytes are not scrambled.
The scrambler can be disabled by setting a bit in the MISC configuration register.
A1/A2 Boundary Refresh
The FWAx control in the register file forces the 8151 to re-write the entire A1/A2 boundary and to refresh
the F6H and 28H bytes while in frame. This feature allows the device to continue to output a valid A1/A2
boundary if input data suddenly disappears, and AIS has not been initiated. In the event that the incoming data
disappears, a valid A1/A2 will still appear in the historical frame boundary location, allowing downstream
devices to remain in frame until AIS can be initiated.
AIS Generation
The VSC8151 can be configured to output a section level AIS stream in lieu of passing SONET/SDH data
received from the RXSIN and RXSCLKIN inputs. This is typically done during LOS or LOF conditions to relay
information about the failure by utilizing the section DCC bytes and keep the downstream sections in-frame and
monitored while fault isolation to takes place.
Setting the AISMODE configuration register replaces the received data stream with an internally generated
AIS-L signal appropriate for section terminating equipment. This signal contains user-defined section overhead
and an all-1’s pattern for the remainder of the bytes (R6-163), conveniently generating AIS for all higher
SONET/SDH alarm levels. The section and line overhead bytes can be modified during AIS in the same manner
that they may in a non-AIS mode.
During the AIS state, the relative A1/A2 boundary can be preserved so that downstream devices will not be
forced to reframe on a new signal. By using the A1/A2 bounder refresh (previous paragraph), the user can ini-
tiate a seamless AIS transition without forcing downstream nodes to enter SEF and frame search state.
Initialization & Configuration
Upon power up of the VSC8151, the user should apply a positive pulse to the system reset pin (SYSRST)
for at least 32 high speed (2.4GHz) clock cycles (12.8ns). Pulsing SYSRST resets all the counters, synchroniz-
ers and state machines used by the 8151.
The device must also be configured upon startup by properly setting the TEST, RATE_SEL, FRMDET,
AIS_MODE, and MISC registers (See Table 2) using the overhead write interface. TEST must be initialized to
an 00H pattern for proper operation. The TXOHWI bit should be set appropriately for all 27 overhead modifica-
tion registers. No default state exists for all configuration and overhead registers, they must be initialized upon
startup. The PT bit of the MISC register has the effect of making the VSC8151 non-intrusive and function as if
in a monitor only mode by internally asserting all TXOHWI bits.
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© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52225-0, Rev. 2.9
12/1/99
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