VSC8163QR データシートの表示（PDF） - Vitesse Semiconductor

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VSC8163QR

OC-48 16:1 SONET/SDH MUX with Clock Generator

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC8163

OC-48 16:1 SONET/SDH

MUX with Clock Generator

Figure 2: Enabling FIFO Operation

PLL locked to reference clock.

RESET

Minimum 5 CLK16 cycles (32ns)

FIFO Mode Operation

Transparent Mode Operation

Holding RESET “low” for a minimum of five CLK16 cycles, then setting “high” enables FIFO operation.

Holding RESET constantly “low” bypasses the FIFO for transparent mode operation.

Figure 3: Split-End DC Termination of CLK16O+/-, REFCLKO+/-

VSC8163

VCC

Split-end equivalent termination is Z0 to VTERM

R1 = 125Ω R2 = 83Ω, Zo=50Ω, VTERM= VCC-2V

R1

R1

Zo

Zo

R1||R2 = Z0

R2

R2

VCCR2 + VEER1

R1+R2

= VTERM

VEE

Figure 4: Traditional DC Termination of CLK16O+/-, REFCLKO+/-

VSC8163

Z0

Z0

50Ω

50Ω

VCC-2V

G52216-0, Rev 3.3

01/05/01

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