W27E520 データシートの表示（PDF） - Winbond
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W27E520 Datasheet PDF : 16 Pages
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W27E520
64K × 8 ELECTRICALLY ERASABLE EPROM
GENERAL DESCRIPTION
The W27E520 is a high speed, low power Electrically Erasable and Programmable Read Only
Memory organized as 65,536 × 8 bits. It includes latches for the lower 8 address lines to multiplex
with the 8 data lines. To cooperate with the MCU, this device could save the external TTL
component, also cost and space. It requires only one supply in the range of 4.5V to 5.5V in normal
read mode. The W27E520 provides an electrical chip erase function. It will be a great convenient
when you need to change/update the contents in the device.
FEATURES
• High speed access time: 70/90 nS (max.)
• Read operating current: 20 mA (max.)
• Erase/Programming operating current
30 mA (max.)
• Standby current: 100 µA (max.)
• Unregulated battery power supply range,
4.5V to 5.5V
• +13V erase and programming voltage
PIN CONFIGURATIONS
• High Reliability CMOS Technology
− 2K V ESD Protection
− 200 mA Latchup Immunity
• Fully static operation
• All inputs and outputs directly TTL/CMOS
compatible
• Three-state outputs
• Available packages: 20-pin TSSOP and 20-pin
SOP
BLOCK DIAGRAM
A10
A12
A14
ALE
VDD
OE/VPP
A15
A13
A11
A9
1
20
2
19
3
18
4
17
5 TSSOP 16
6
Top View
15
7
14
8
13
9
12
10
11
A8
AD1
AD3
AD5
AD7
GND
AD6
AD4
AD2
AD0
OE/VPP
A15
A13
A11
A9
AD0
AD2
AD4
AD6
GND
1
20
2
19
3
18
4
17
5 SOP 16
6
Top View
15
7
14
8
13
9
12
10
11
VDD
ALE
A14
A12
A10
A8
AD1
AD3
AD5
AD7
ALE
OE / VPP
CONTROL
OUTPUT
BUFFER
AD7 - AD0
A15 - A8
L
A
T
C
H
E
S
DECODER
VDD
GND
MEMORY
ARRAY
PIN DESCRIPTION
SYMBOL
AD0−AD7
A8−A15
ALE
OE /VPP
VDD
GND
DESCRIPTION
Address/Data Inputs/Outputs
Address Inputs
Address Latch Enable
Output Enable, Program/Erase
Supply Voltage
Power Supply
Ground
Publication Release Date: September 2000
-1-
Revision A2
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