W742E816 データシートの表示（PDF） - Winbond

部品番号

コンポーネント説明

メーカー

W742E816

4-BIT MICROCONTROLLER

Winbond 

W742E/C816

Deleted: SA5505

Deleted: W742C811

5.7 Main Oscillator

The W742E/C816 provides a crystal oscillation circuit to generate the system clock through external

connections. The 3.58 MHz or 400 KHz crystal must be connected to XIN1 and XOUT1, and a

capacitor must be connected to XIN1 and VSS if an accurate frequency is needed.

Crystal

3.58 MHz

XIN1

XOUT1

Figure 5-3. System Clock Oscillator Configuration

5.8 Sub-oscillator

The sub-oscillator is used in dual-clock operation mode. In the sub-oscillator application, just only the

32768 Hz crystal could be connected to XIN2 and XOUT2.

5.9 Dividers

Divider 0 is organized with a 14-bit binary up-counter that is designed to generate periodic interrupt.

When the main clock starts action, the Divider0 is incremented by each clock (FOSC). The main clock

can come from main oscillator or sub-oscillator by setting SCR register. When an overflow occurs, the

Divider0 event flag is set to 1 (EVF.0 = 1). Then, if the Divider0 interrupt enable flag has been set

(IEF.0 = 1), the interrupt is executed, while if the hold release enable flag has been set (HEF.0 = 1),

the hold state is terminated. And the last 4-stage of the Divider0 can be reset by executing CLR

DIVR0 instruction. If the main clock is connected to the 32.768 KHz crystal, the EVF.0 will be set to 1

periodically at the period of 500 mS.

Divider 1 is orginized with 13/12 bits up-counter that only has sub-oscillator clock source. If the sub-

oscillator starts action, the Divider1 is incremented by each clock (Fs). When an overflow occurs, the

Divider1 event flag is set to 1 (EVF.4 = 1). Then, if the Divider1 interrupt enable flag has been set

(IEF.4 = 1), the interrupt is executed, while if the hold release enable flag has been set (HEF.4 = 1),

the hold state is terminated. And the last 4-stage of the Divider1 can be reset by executing CLR

DIVR1 instruction. There are two period time (125 mS & 250 mS) that can be selected by setting the

SCR.3 bit. When SCR.3 = 0 (default), the 250 mS period time is selected; SCR.3 = 1, the 125 mS

period time is selected.

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