W742E816 データシートの表示（PDF） - Winbond

部品番号

コンポーネント説明

メーカー

W742E816

4-BIT MICROCONTROLLER

Winbond 

W742E/C816

Deleted: SA5505

Deleted: W742C811

5.10 Dual-clock Operation

In this dual-clock mode, the normal operation is performed by generating the system clock from the

main-oscillator clock (Fm). As required, the slow operation can be performed by generating the system

clock from the sub-oscillator clock (Fs). The exchange of the normal operation and the slow operation

is performed by setting the bit 0 of the System clock Control Register (SCR). If the SCR.0 is set to 0,

the clock source of the system clock generator is main-oscillator clock; if the SCR.0 is set to 1, the

clock source of the system clock generator is sub-oscillator clock. In the dual-clock mode, the main-

oscillator can stop oscillating when the SCR.1 is set to 1. When the main clock switch, we must care

the following cases:

1. X000B → X011B (FOSC = Fm→ FOSC = Fs): we should not exchange the FOSC from Fm into Fs and

disable Fm simultaneously. We could first exchange the FOSC from Fm into Fs, then disable the

main-oscillator. So it should be X000B→X001B→X011B.

2. X011B → X000B (FOSC = Fs→ FOSC = Fm): we should not enable Fm and exchange the FOSC from

Fs into Fm simultaneously. We could first enable the main-oscillator; the 2nd step is calling a delay

subroutine to wait the main-oscillator oscillating stabely; then exchange the FOSC from Fs into Fm

is the last step. So it should be X011B→X001B→delay the Fm oscillating stable time→X000B.

We must remember that the X010B state is inhibitive, because it will induce the system shutdown.

The organization of the dual-clock operation mode is shown in Figure 5-4.

HOLD

SCR.0

XIN1

XOUT1

Fm

Main Oscillator

Fosc

System Clock

T1

T2

Fs

Generator

T3

SCR.1 enable/disable

T4

STOP

Divider 0

XIN2

XOUT2

Sub-oscillator

LCD Frequency

Selector

Divider 1

INT4

HCF.4

SCR: System clock Control Register (default = 00H)

SCR.3(13/12 bit)

Bit3 Bit2 Bit1 Bit0

0 : Fosc = Fm

1 : Fosc = Fs

0 : Fm enable

1 : Fm disable

0 : WDT input clock is Fosc/1024

1 : WDT input clock is Fosc/16384

0 : 13 bit

1 : 12 bit

Daul clock operation mode:

- SCR.0 = 0, Fosc = Fm: SCR.0 = 1, Fosc = Fs

- Flcd = Fs, In STOP mode LCD is turned off.

FLCD

Figure 5-4. Organization of the dual-clock operation mode

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Publication Release Date: April 15, 2005

Revision A2

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