W83176R-735 データシートの表示（PDF） - Winbond

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W83176R-735

3 DIMM DDR ZERO DELAY BUFFER

Winbond 

W83176R-735/W83176G-735

3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET

1. GENERAL DESCRIPTION

The W83176R-735 is a 2.5V Zero-delay D.D.R. Clock buffer designed for SiS system. W83176R-735

can support 3 D.D.R. DRAM DIMMs.

The W83176R-735 provides I2C serial bus interface to program the registers to enable or disable each

clock outputs. The W83176R-735 accepts a reference clock as its input and runs on 2.5V supply.

2. PRODUCT FEATURES

• Zero-delay clock outputs

• Feedback pins for synchronous

• Supports up to 3 D.D.R. DIMMs

• One pairs of additional outputs for feedback

• Low Skew outputs (< 100ps)

• Supports 400MHz D.D.R. SDRAM

• I2C 2-Wire serial interface and supports Byte or Block Date RW

• 48-pin SSOP package

3. PIN CONFIGURATION

GND 1

C LK C 0 2

C LK T0 3

VDD 4

C LK T1 5

C LK C 1 6

GND 7

GND 8

C LK C 2 9

C LK T2 10

V D D 11

* S C LK 12

C L K _ IN T 1 3

N /C 1 4

V D D 15

A V D D 16

A G N D 17

G N D 18

C LK C 3 19

C LK T3 20

V D D 21

C LK T4 22

C LK C 4 23

G N D 24

*: Internal pull-up resistor 120K to VDD

48 G N D

47 C LK C 5

46 C LK T5

45 V D D

44 C LK T6

43 C LK C 6

42 G N D

41 G N D

40 C LK C 7

39 C LK T7

38 V D D

37 S D A TA *

3 6 N /C

3 5 F B _ IN T

34 V D D

33 FB _O U TT

32 N C

31 G N D

30 C LK C 8

29 C LK T8

28 V D D

27 C LK T9

26 C LK C 9

25 G N D

Publication Release Date: March 31, 2006

-1-

Revision 1.1

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