W986416DH データシートの表示（PDF） - Winbond
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W986416DH Datasheet PDF : 48 Pages
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W986416DH
5. PIN DESCRIPTION
PIN NUMBER PIN NAME FUNCTION
DESCRIPTION
23 − 26, 22, A0 − A11 Address
Multiplexed pins for row and column address.
29 − 35
Row address: A0 − A11. Column address: A0 − A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank
selected by BS0, BS1.
20, 21
BS0, BS1 Bank Select
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
2, 4, 5, 7, 8,
10, 11, 13, 42,
44, 45, 47, 48,
50, 51, 53
DQ0 −
DQ15
Data Input/
Output
Multiplexed pins for data output and input.
19
CS Chip Select
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
18
RAS Row Address Command input. When sampled at the rising edge of
Strobe
the clock RAS , CAS and WE define the
operation to be executed.
17
CAS Column
Referred to RAS
Address Strobe
16
WE Write Enable Referred to RAS
39, 15
38
37
1, 14, 27
28, 41, 54
3, 9, 43, 49
6, 12, 46, 52
36, 40
UDQM
LDQM
CLK
CKE
VCC
VSS
VCCQ
VSSQ
NC
Input/output
Mask
Clock Inputs
Clock Enable
Power (+3.3V)
Ground
Power (+3.3V)
for I/O Buffer
Ground for I/O
Buffer
No Connection
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
System clock used to sample inputs on the rising edge
of clock.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside DRAM.
Separated power from VCC, to improve DQ noise
immunity.
Separated ground from VSS, to improve DQ noise
immunity.
No connection
Publication Release Date: April 11, 2002
-5-
Revision A4
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