WF128K16-60CM5 データシートの表示（PDF） - Unspecified
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WF128K16-60CM5 Datasheet PDF : 11 Pages
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WF128K16, WF256K16-XCX5
5V FLASH MODULE PRELIMINARY *
FEATURES
s Access Times of 50, 60, 70, 90, 120 and 150ns
s 40 pin Ceramic DIP (Package 303)
s Organized as 128Kx16 and 256Kx16
s Sector Architecture
• 8 equal size sectors of 16KBytes each per chip
• Any combination of sectors can be concurrently erased.
Also supports full chip erase
s 100,000 Erase/Program Cycles Minimum (0°C to 70°C)
s Data Retention, 10 Years at 125°C
s Commercial, Industrial and Military Temperature Ranges
s 5 Volt Programming; 5V ±10% Supply
s Low Power CMOS
s Embedded Erase and Program Algorithms
s TTL Compatible Inputs and CMOS Outputs
s Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
s Page Program Operation and Internal Program Control Time
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
Note: Programming information available upon request.
FIG. 1 PIN CONFIGURATION AND BLOCK DIAGRAM
TOP VIEW
CS2*/NC 1
CS1 2
I/O15 3
I/O14 4
I/O13 5
I/O12 6
I/O11 7
I/O10 8
I/O9 9
I/O8 10
GND 11
I/O7 12
I/O6 13
I/O5 14
I/O4 15
I/O3 16
I/O2 17
I/O1 18
I/O0 19
OE 20
40 VCC
39 WE
38 A16
37 A15
36 A14
35 A13
34 A12
33 A11
32 A10
31 A9
30 GND
29 A8
28 A7
27 A6
26 A5
25 A4
24 A3
23 A2
22 A1
21 A0
* CS2 for 256Kx16 and NC for 128Kx16
PIN DESCRIPTION
A0-16
I/O0-15
CS1-2
OE
WE
VCC
GND
Address Inputs
Data Input/Output
Chip Selects
Output Enable
Write Enable
+5.0V Power
Ground
7
BLOCK DIAGRAM
FOR WF256K16-XCX5
I/O0-7
I/O8-15
BLOCK DIAGRAM
FOR WF128K16-XCX5
WE
OE
A0-16
WE
OE
A0-16
I/O0-7
I/O8-15
128K x 8
128K x 8
128K x 8
128K x 8
128K x 8
128K x 8
CS1
C S 1(1)
C S 2(1)
NOTE:
1. CS1 and CS2 are used to select the lower and upper 128Kx16 of the
device. CS1 and CS2 must not be enabled at the same time.
October 1998
1
White Microelectronics • Phoenix, AZ • (602) 437-1520
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