WF4M16-120DTC5 データシートの表示（PDF） - White Electronic Designs Corporation

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WF4M16-120DTC5

2x2Mx16 5V FLASH MODULE

White Electronic Designs Corporation 

WF4M16-XDTX5

HI-RELIABILITY PRODUCT

2x2Mx16 5V FLASH MODULE ADVANCED*

FEATURES

s Access Time of 90, 120, 150ns

s Packaging:

• 56 Lead, Hermetic Ceramic, 0.520" CSOP (Package 213).

Fits standard 56 SSOP footprint.

s Sector Architecture

• 32 equal size sectors of 64KBytes per each 2Mx8 chip

• Any combination of sectors can be erased. Also supports

full chip erase.

s Minimum 100,000 Write/Erase Cycles Minimum

s Organized as two banks of 2Mx16; User Configurable as

4 x 2Mx8

s Commercial, Industrial, and Military Temperature Ranges

s 5 Volt Read and Write. 5V ± 10% Supply.

s Low Power CMOS

s Data Polling and Toggle Bit feature for detection of program

or erase cycle completion.

s Supports reading or programming data to a sector not being

erased.

s Built-in Decoupling Caps and Multiple Ground Pins for Low

Noise Operation, Separate Power and Ground Planes to

improve noise immunity

s RESET pin resets internal state machine to the read mode.

s Ready/Busy (RY/BY) output for direction of program or erase

cycle completion.

* This data sheet describes a product that may or may not be under

development and is subject to change or cancellation without notice.

Note: For programming information refer to Flash Programming 16M5

Application Note.

FIG. 1 PIN CONFIGURATION FOR WF4M16-XDTX5

56 CSOP

TOP VIEW

CS1 1

A12 2

A13 3

A14 4

A15 5

NC 6

CS2 7

NC 8

A20 9

A19 10

A18 11

A17 12

A16 13

VCC 14

GND 15

I/O6 16

I/O14 17

I/O7 18

I/O15 19

RY/BY 20

OE 21

WE 22

NC 23

I/O13 24

I/O5 25

I/O12 26

I/O4 27

VCC 28

56 NC

55 RESET

54 A11

53 A10

52 A9

51 A1

50 A2

49 A3

48 A4

47 A5

46 A6

45 A7

44 GND

43 A8

42 VCC

41 I/O9

40 I/O1

39 I/O8

38 I/O0

37 A0

36 NC

35 CS3

34 CS4

33 I/O2

32 I/O10

31 I/O3

30 I/O11

29 GND

PIN DESCRIPTION

BLOCK DIAGRAM

I/O0-15 Data Inputs/Outputs

A0-20

Address Inputs

I/O0-7

I/O8-15

WE

Write Enable

RESET

WE

OE

A0-20

RY/BY

CS1-4

OE

VCC

Chip Selects

Output Enable

Power Supply

2M x 8

2M x 8

2M x 8

2M x 8

GND

RY/BY

Ground

Ready/Busy

CS1

RESET

Reset

CS2

CS3

CS4

NOTE:

1. RY/BY is an open drain output and should be pulled-up to Vcc with an

external resistor.

2. CS1 and CS3 control the same data bus. Reads cannot be done with CS1

and CS3 both active. CS2 and CS4 control the same data bus. Reads

cannot be done with CS2 and CS4 both active.

3. Address compatible with Intel 2M8 56 SSOP.

November 1999 Rev.3

1

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

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