WM8718 データシートの表示（PDF） - Wolfson Microelectronics plc
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WM8718 Datasheet PDF : 32 Pages
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WM8718
3-WIRE SERIAL CONTROL INTERFACE TIMING
LATCH
SCLK
tSCY
tSCH
tSCL
Production Data
tCSL
tCSH
tCSS
tSCS
SDIN
tDSU
tDHO
LSB
Figure 3 Program Register Input Timing - 3-Wire Serial Control Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
Program Register Input Information
SCLK rising edge to LATCH
tSCS
rising edge
SCLK pulse cycle time
tSCY
SCLK pulse width low
tSCL
SCLK pulse width high
tSCH
SDIN to SCLK set-up time
tDSU
SCLK to SDIN hold time
tDHO
LATCH pulse width low
tCSL
LATCH pulse width high
tCSH
LATCH rising to SCLK rising
tCSS
TEST CONDITIONS
MIN
TYP
MAX
40
80
20
20
20
20
20
20
20
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
w
PD Rev 4.3 November 2006
11
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