WM8756 データシートの表示（PDF） - Wolfson Microelectronics plc
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WM8756 Datasheet PDF : 39 Pages
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WM8756
DSD AUDIO BIPHASE INTERFACE
Advance Information
DSDCLK64
DSDCLK128
DSD[0:5]
tDIFF
tBDCY64
tBDCH
tBDCL
inverse D(n-1)
D(n)
tBDS
tBDH
tBDCY128
inverse D(n)
Figure 4 DSD Audio Data Timing - Phase Modulation Mode
Test Conditions
AVDD= DVDD = 5V, AGND= GR= DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
DSDCLK64 cycle time
DSDCLK128 cycle time
DSDCLK128 pulse width
high
tBDCY64
tBDCY128
tBDCH
DSDCLK128 pulse width
low
tBDCL
DSD[0:5] set-up time to
tBDS
DSDCLK128 rising edge
DSD[0:5] hold time from
tBDH
DSDCLK128 rising edge
Difference in edge timing of
tDIFF
DSDCLK64 to DSDCLK128
TEST CONDITIONS
MIN
TYP
MAX
354.4
177.2
80
80
10
10
20
Table 9 DSD Digital Audio Timing
UNIT
ns
ns
ns
ns
ns
ns
ns
AI Rev 1.3 October 2001
10
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