WM8781 データシートの表示（PDF） - Wolfson Microelectronics plc
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WM8781 Datasheet PDF : 20 Pages
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AUDIO INTERFACE TIMING – SLAVE MODE
WM8781
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
Audio Data Input Timing Information
SYMBOL
MIN
TYP
MAX
BCLK cycle time
tBCY
50
BCLK pulse width high
tBCH
20
BCLK pulse width low
tBCL
20
LRCLK set-up time to BCLK rising edge
tLRSU
10
LRCLK hold time from BCLK rising edge
tLRH
10
DOUT propagation delay from BCLK falling edge
tDD
0
10
Table 3 Digital Audio Data Timing - Slave Mode
UNIT
ns
ns
ns
ns
ns
ns
Note:
LRCLK should be synchronous with MCLK, although the WM8781 interface is tolerant of phase variations or jitter on these
signals.
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PD, April 2006, Rev 4.1
9
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