WM8782 データシートの表示（PDF） - Wolfson Microelectronics plc

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WM8782

24-Bit, 192kHz Stereo ADC

Wolfson Microelectronics plc 

WM8782

Production Data

SLAVE MODE MCLK / BCLK TIMING

A

B

MCLK1

V_LOW

BCLK

V_LOW

MCLK2

V_HI

D

Keep-out area for MCLK/BCLK relationship

C

Figure 4 MCLK / BCLK prohibited timing relationship in slave mode

TIMING

A

B

C

D

TIME (ns)

9

4

9

4

Table 4 Prohibited area timings

DESCRIPTION

MCLK falling edge to BCLK falling edge keep-out window

MCLK rising edge to BCLK falling edge keep-out window

In slave mode operation, there are two windows where the BCLK falling edge relative to the MCLK

falling/rising edge is not allowed, as defined in Figure 4 and Table 4. Any device with clocks operating

in this area may cause incorrect operation of the ADC, as detailed in WTR0444.

This specification is guaranteed by design rather than test, and the timings are related to the

switching level of the MCLK and BCLK pads. Simulation has shown the switching level range for both

the MCLK and BCLK pads across process, voltage and temperature to be as per the table below.

SWITCHING LEVEL

MIN (V)

V_LOW

1.1

V_HI

1.3

Table 5 Simulated switching area range

MAX (V)

1.4

1.6

If the above timing constraints cannot be met in slave mode, it is recommended that WM8782A

silicon is used in place of WM8782.

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PD, April 2010, Rev 4.7

10

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