WM8782 データシートの表示（PDF） - Wolfson Microelectronics plc

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WM8782

24-Bit, 192kHz Stereo ADC

Wolfson Microelectronics plc 

WM8782

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

Production Data

Figure 1 System Clock Timing Requirements

Test Conditions

DVDD = 3.3V, DGND = 0V, TA = +25oC, fs = 48kHz, Slave Mode, MCLK = 256fs, 24-bit data, unless otherwise stated.

PARAMETER

System Clock Timing Information

MCLK System clock pulse width high

MCLK System clock pulse width low

MCLK System clock cycle time

MCLK duty cycle

SYMBOL

TMCLKL

TMCLKH

TMCLKY

TMCLKDS

MIN

11

11

28

40:60

TYP

MAX

60:40

Table 1 Master Clock Timing Requirements

UNIT

ns

ns

ns

AUDIO INTERFACE TIMING – MASTER MODE

Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)

Test Conditions

DVDD = 3.3V, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.

PARAMETER

Audio Data Input Timing Information

LRCLK propagation delay from BCLK falling edge

DOUT propagation delay from BCLK falling edge

SYMBOL

tDL

tDDA

MIN

TYP

MAX

0

10

0

10

Table 2 Digital Audio Data Timing – Master Mode

UNIT

ns

ns

w

PD, April 2010, Rev 4.7

8

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