WM8782 データシートの表示（PDF） - Wolfson Microelectronics plc
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WM8782 Datasheet PDF : 20 Pages
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AUDIO INTERFACE TIMING – SLAVE MODE
WM8782
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
Audio Data Input Timing Information
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
LRCLK set-up time to BCLK rising edge
LRCLK hold time from BCLK rising edge
DOUT propagation delay from BCLK falling edge
SYMBOL
tBCY
tBCH
tBCL
tLRSU
tLRH
tDD
MIN
TYP
MAX
50
20
20
10
10
0
10
Table 3 Digital Audio Data Timing – Slave Mode
UNIT
ns
ns
ns
ns
ns
ns
Note:
LRCLK should be synchronous with MCLK.
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PD, April 2010, Rev 4.7
9
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