WM8785 データシートの表示（PDF） - Wolfson Microelectronics plc
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WM8785 Datasheet PDF : 31 Pages
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Production Data
AUDIO INTERFACE TIMING – SLAVE MODE, PCM DATA
WM8785
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
Audio Data Input Timing Information
BCLK cycle time
LRCLK set-up time to BCLK rising edge
LRCLK hold time from BCLK rising edge
DOUT propagation delay from BCLK falling edge
SYMBOL
tBCY
tLRSU
tLRH
tDD
MIN
TYP
MAX
UNIT
25
ns
10
ns
10
ns
0
11
ns
CONTROL INTERFACE TIMING – 3-WIRE MODE
CSB
tCSL
SCLK
tSCY
tSCH
tSCL
tCSH
tSCS
tCSS
SDIN
tDSU
tDHO
LSB
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
DVDD = 3.3V, DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise
stated.
PARAMETER
Program Register Input Information
SCLK rising edge to CSB rising edge
SCLK pulse cycle time
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
CSB pulse width low
CSB pulse width high
CSB rising to SCLK rising
Pulse width of spikes that will be suppressed
SYMBOL
tSCS
tSCY
tSCL
tSCH
tDSU
tDHO
tCSL
tCSH
tCSS
tps
MIN
TYP
MAX
UNIT
80
ns
200
ns
80
ns
80
ns
40
ns
40
ns
40
ns
40
ns
40
ns
4
6
ns
w
PD Rev 4.1 December 2006
9
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