WM8788 データシートの表示（PDF） - Wolfson Microelectronics plc

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WM8788

High Performance 24-bit Stereo ADC

Wolfson Microelectronics plc 

WM8788

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

MCLK

Preliminary Technical Data

tMCLKY

tMCLKL tMCLKH

Figure 2 Master Clock Timing

Test Conditions

AVDD = REFVDD = 3.3V, AGND = 0V, TA = +25oC.

PARAMETER

Master Clock Timing

MCLK frequency

MCLK duty cycle

(= TMCLKH : TMCLKL)

SYMBOL

1 / TMCLKY

CONDITIONS

MIN

2.048

60:40

TYP

MAX

UNIT

36.864

40:60

MHz

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PTD, December 2010, Rev 2.2

8

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