WM8788 データシートの表示（PDF） - Wolfson Microelectronics plc

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WM8788

High Performance 24-bit Stereo ADC

Wolfson Microelectronics plc 

Preliminary Technical Data

AUDIO INTERFACE TIMING

MASTER MODE

BCLK

(output)

LRCLK

(output)

ADCDAT

(output)

WM8788

tDL

tDDA

Figure 3 Audio Interface Timing - Master Mode

Test Conditions

AVDD = REFVDD = 3.3V, AGND = 0V,

TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated.

PARAMETER

Audio Interface Timing - Master Mode

LRCLK propagation delay from BCLK falling edge

ADCDAT propagation delay from BCLK falling edge

SYMBOL

MIN

TYP

MAX

UNIT

tDL

20

ns

tDDA

20

ns

SLAVE MODE

Figure 4 Audio Interface Timing - Slave Mode

Test Conditions

AVDD = REFVDD = 3.3V, AGND = 0V,

TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated.

PARAMETER

Audio Interface Timing - Slave Mode

BCLK cycle time

BCLK pulse width high

BCLK pulse width low

LRCLK set-up time to BCLK rising edge

LRCLK hold time from BCLK rising edge

ADCDAT propagation delay from BCLK falling edge

SYMBOL

tBCY

tBCH

tBCL

tLRSU

tLRH

tDD

MIN

50

20

20

20

20

w

TYP

MAX

UNIT

ns

ns

ns

ns

ns

20

ns

PTD, December 2010, Rev 2.2

9

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