WM8945ECS データシートの表示（PDF） - Wolfson Microelectronics plc

部品番号

コンポーネント説明

メーカー

WM8945ECS

Mono Low-Power CODEC with Video Buffer and Touch Panel Controller

Wolfson Microelectronics plc 

WM8945

Production Data

TABLE OF CONTENTS

DESCRIPTION....................................................................................................... 1

FEATURES ............................................................................................................ 1

APPLICATIONS..................................................................................................... 1

TABLE OF CONTENTS......................................................................................... 2

BLOCK DIAGRAM ................................................................................................ 5

PIN CONFIGURATION .......................................................................................... 6

ORDERING INFORMATION.................................................................................. 6

PIN DESCRIPTION................................................................................................ 7

ABSOLUTE MAXIMUM RATINGS ........................................................................ 8

RECOMMENDED OPERATING CONDITIONS..................................................... 8

THERMAL PERFORMANCE................................................................................. 9

ELECTRICAL CHARACTERISTICS ................................................................... 10

TERMINOLOGY ............................................................................................................. 13

TYPICAL PERFORMANCE ................................................................................. 14

POWER CONSUMPTION .............................................................................................. 15

AUDIO SIGNAL PATHS DIAGRAM .................................................................... 16

SIGNAL TIMING REQUIREMENTS .................................................................... 17

SYSTEM CLOCK TIMING.............................................................................................. 17

AUDIO INTERFACE TIMING ......................................................................................... 17

MASTER MODE ........................................................................................................................................ 17

SLAVE MODE ........................................................................................................................................... 18

CONTROL INTERFACE TIMING ................................................................................... 19

DEVICE DESCRIPTION ...................................................................................... 22

INTRODUCTION ............................................................................................................ 22

ANALOGUE INPUT SIGNAL PATH ............................................................................... 23

INPUT PGA ENABLE ................................................................................................................................ 24

INPUT PGA CONFIGURATION ................................................................................................................ 24

MICROPHONE BIAS CONTROL .............................................................................................................. 25

INPUT PGA GAIN CONTROL ................................................................................................................... 25

DIGITAL MICROPHONE INTERFACE .......................................................................... 27

ANALOGUE-TO-DIGITAL CONVERTER (ADC)............................................................ 28

ADC VOLUME CONTROL......................................................................................................................... 28

ADC HIGH PASS FILTER ......................................................................................................................... 31

DSP CORE..................................................................................................................... 32

DSP CONFIGURATION MODES .............................................................................................................. 32

LOW-PASS / HIGH-PASS FILTER (LPF/HPF).......................................................................................... 33

5-NOTCH FILTER ..................................................................................................................................... 34

DF1 FILTER............................................................................................................................................... 35

RETUNETM FILTER ................................................................................................................................... 35

5-BAND EQ ............................................................................................................................................... 36

DYNAMIC RANGE CONTROL (DRC) ....................................................................................................... 36

SIGNAL ENHANCEMENT REGISTER CONTROLS................................................................................. 36

DYNAMIC RANGE CONTROL (DRC) ........................................................................... 37

DRC COMPRESSION / EXPANSION / LIMITING..................................................................................... 38

GAIN LIMITS ............................................................................................................................................. 40

GAIN READBACK ..................................................................................................................................... 41

DYNAMIC CHARACTERISTICS ............................................................................................................... 42

ANTI-CLIP CONTROL...............................................................................................................................43

QUICK-RELEASE CONTROL ................................................................................................................... 44

DRC INITIAL VALUE ................................................................................................................................. 44

w

PD, May 2011, Rev 4.1

2

Share Link: