TDA7535 データシートの表示（PDF） - STMicroelectronics

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TDA7535

Delta/sigma cascade 20 bit stereo DAC

STMicroelectronics 

I2S interface

TDA7535

Table 10. Timing characteristics (continued)

Timing

Description

Min.

Max.

tsckr SCK rise time

22

tsckf SCK fall time

20

1. SCK clock defines the Fs, being the Sample Rate. This input clock needs a jitter below ~212psRMS.

2. FSYNC switches inside the time window as specified w.r.t. to falling edge of SCK.

Figure 5. Power up and reset sequence

Unit

ns

ns

VDD

uct(s) RESET

TRES

Obsolete Product(s) - Obsolete Prod Figure 6. Frequency response

TRES

Min 50ms

D02AU1418

8/12

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