X24C04-2.7 データシートの表示（PDF） - Xicor -> Intersil

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X24C04-2.7

Serial EEPROM

Xicor -> Intersil 

X24C04

Figure 3. Acknowledge Response From Receiver

SCL From

Master

1

Data Output

From Transmitter

8

9

Data Output

From Receiver

START

Acknowledge

DEVICE ADDRESSING

Following a start condition the master must output the

address of the slave it is accessing. The most signifi-

cant four bits of the slave are the device type identifier

(see Figure 4). For the X24C04 this is fixed as 1010[B].

Figure 4. Slave Addressing

Device Type

Identifier

Device High Order

Address Word Address

1 0 1 0 A2 A1 A0 R/ W

The next two significant bits address a particular

device. A system could have up to four X24C04

devices on the bus (see Figure 10). The four addresses

are defined by the state of the A1 and A2 inputs.

The next bit of the slave address is an extension of the

array’s address and is concatenated with the eight bits

of address in the word address field, providing direct

access to the whole 512 x 8 array.

Note: This bit is part of word address. Not related to

device address pin A0.

The last bit of the slave address defines the operation to

be performed. When set to one a read operation is

selected, when set to zero a write operation is selected.

Following the start condition, the X24C04 monitors the

SDA bus comparing the slave address being transmit-

ted with its slave address (device type and state of A1

and A2 inputs). Upon a correct compare the X24C04

outputs an acknowledge on the SDA line. Depending

on the state of the R/W bit, the X24C04 will execute a

read or write operation.

WRITE OPERATIONS

Byte Write

For a write operation, the X24C04 requires a second

address field. This address field is the word address,

comprised of eight bits, providing access to any one of

the 512 words of memory. Upon receipt of the word

address the X24C04 responds with an acknowledge,

and awaits the next eight bits of data, again responding

with an acknowledge. The master then terminates the

transfer by generating a stop condition, at which time

the X24C04 begins the internal write cycle to the non-

volatile memory. While the internal write cycle is in

progress the X24C04 inputs are disabled, and the

device will not respond to any requests from the mas-

ter. Refer to Figure 5 for the address, acknowledge and

data transfer sequence.

REV 1.1.3 11/28/00

www.xicor.com

Characteristics subject to change without notice. 4 of 13

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